chip-design
Chip_Design
AURA-1: designing an edge-AI chip for a neckband headphone
Working files from a solo, from-scratch attempt to specify and prototype an
edge-AI inference SoC for wireless neckband headphones: a resident,
speech-native conversational model on the device, the cloud called as a tool for
facts. The novel block is the NPU; Wi-Fi, Bluetooth, codec, ANC and PMU are
sourced, not designed.
The author is a process engineer learning chip design. The archive is
deliberately complete: the… See the full description on the dataset page: https://huggingface.co/datasets/sangramrout/Chip_Design.semiconductor-rtl-verilog-chip-design-2026
⚡ Complete 2026 Semiconductor & RTL/Verilog Chip Design SFT & DPO Suite
An industry-first, production-grade reasoning and alignment corpus specifically engineered for fine-tuning Large Language Models on synthesizable SystemVerilog, FPGA/ASIC hardware design, and silicon signoff verification.
This release provides 1,000 verified preview pairs (from the complete 10,000 SFT & 2,500 DPO master suite) spanning 20 mission-critical silicon IP architectures, audited against IEEE… See the full description on the dataset page: https://huggingface.co/datasets/beatsprom/semiconductor-rtl-verilog-chip-design-2026.Graphbench_Chipdesign