Verilog
VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUFVeriReason-Qwen2.5-3B-Verilog-RTL-GRPO-reasoning-tb-GGUFVeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUFQwen-2.5-Instruct-Unverified-Verilog-Reasoning-GT-7B-GGUFVeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUFQwen-2.5-Instruct-Unverified-Verilog-GEN-7B-GGUFVeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUFqwen2.5-coder-32b-single-verilog-i1-GGUF
Datasets
All datasets matching “Verilog”verilog_data-1verilog_data-2verilog_data-3Verilog_GitHub
VeriGen
Dataset Summary
The dataset comprises Verilog modules as entries. The entries were retrieved from the GitHub dataset on BigQuery.
For training [models (https://huggingface.co/shailja/fine-tuned-codegen-2B-Verilog)], we filtered entries with no of characters exceeding 20000 and duplicates (exact duplicates ignoring whitespaces).
Paper: Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Point of Contact: contact@shailja
Languages:… See the full description on the dataset page: https://huggingface.co/datasets/shailja/Verilog_GitHub.MG-Verilog
Dataset Card for MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation
Authors: Yongan Zhang, Zhongzhi Yu, Yonggan Fu, Cheng Wan, Yingyan (Celine) Lin
Dataset Summary
This dataset is the dataset generated in our paper: MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation.
In this work, we aim to mitigate the limitations of existing datasets for LLM-assisted hardware design by proposing our open-sourced… See the full description on the dataset page: https://huggingface.co/datasets/GaTech-EIC/MG-Verilog.verilog-instruct-60k