hardware-fab/DFS_DESYNCH

DFS_DESYNCH

The DFS_DESYNCH dataset contains power traces of a software AES implementation running on a 32-bit RISC-V System-on-Chip (SoC). The SoC incorporates a Dynamic Frequency Scaling (DFS) unit that randomly adjusts the operating frequency between 35MHz and 60MHz.

• —Curated by: hardware-fab
• —License: Open Data Commons License cc-by-4.0
• —Repository: DLaTA methodology GitHub
• —Paper: A Deep Learning-assisted Template Attack Against Dynamic Frequency Scaling Countermeasures

The dataset is designed to aid research in side-channel analysis methodologies. DFSDESYNCH was created to support the DLaTA methodology [[1]](https://huggingface.co/datasets/hardware-fab/DFSDESYNCH#note) for resynchronizing power traces collected under frequency scaling. The code for DLaTA is publicly available on GitHub.

How to Download

1. 1.Download dataset. ⚠ WARNING: Full dataset requires 205 GB of space.

    from huggingface_hub import snapshot_download

    snapshot_download(repo_id="hardware-fab/DFS_DESYNCH", repo_type="dataset", local_dir="<download_path>")

1. 1.Assemble dataset chunks in one (virtual) dataset file.

    python assemble.py --dataset_dir <download_path>

Replace <download_path> with the actual download path. The assemble.py script is downloaded along with the data.

Dataset Structure

The dataset has the following structure:

• —Profiling and Attack groups: The traces are separated into two main groups: "profiling" and "attack". Each group contains 128,000 traces for a total of 256,000 traces.
• —Three Datasets per group: Each group ("profiling" and "attack") consists of three internal datasets:
• —traces: This dataset includes 128,000 power traces, each containing 200,000 time samples. The traces capture the entire AES encryption process preceded by a sequence of random instructions. The traces are pre-processed with a high-pass filter with a 125 kHz cut-off frequency.
• —labels: This dataset provides labels for each power trace in the "traces" dataset, indicating the frequency changes that occurred during the measurement. Each label has two fields:
• —sample: This field denotes the time sample at which a frequency change happens, with values ranging from 0 to 200,000.
• —frequency: This field specifies the new operating frequency starting from the corresponding sample. It can take values from the set {35, 40, 45, 50, 55, 60}.
• —metadata: This dataset contains metadata for each trace, including two members:
• —key: The secret key used for AES encryption.
• —plaintext: The plaintext used for the AES encryption.

Dataset Format

The dataset is stored in the HDF5 file format. To alleviate the size of the file, we partitioned the dataset into 32 files based on the cryptographic key. Keys are 16-byte arrays, we vary only the first byte keeping the remaining 15 fixed.

Following the structure of the dataset, below are HDF5 fields used and their atomic type:

.  
├── profiling  
│    ├── traces [float32]
│    ├── labels [('sample', uint32), ('frequency', uint32)]  
│    └── metadata [('key', np.uint8, (16,)), ('plaintext', np.uint8, (16,))]
└── attack  
     ├── traces [float32]
     ├── labels [('sample', uint32), ('frequency', uint32)]  
     └── metadata [('key', np.uint8, (16,)), ('plaintext', np.uint8, (16,))]    

Dataset Collection

The data are collected from a real-world hardware-software infrastructure. The setup comprises a host PC, a Picoscope 5244d digital sampling oscilloscope (DSO), and a NewAE CW305 board which hosts an AMD Artix-7 FPGA. The board is specifically designed to facilitate the deployment of digital designs targeting FPGAs and studying their side-channel behavior. The sampling rate of the DSO is set to 125Msample/s with a resolution of 12 bits for the entire dataset.

The FPGA implements a system-on-chip consisting of a 1.5Mps UART interface to communicate with the host, an in-order 32-bit RISC-V CPU to execute the user applications, a CLKLBLGEN unit to label the operating frequency digitally, and a DFS actuator to change the operating frequency at runtime. The DFS actuator is instructed to change the operating frequency of the computing platform randomly at its maximum speed.

As the cryptographic operation of choice, we selected the OpenSSL AES implementation, representing the standard for symmetric cryptography.

Social Impact of Dataset

DFSDESYNCH has been developed to enhance side-channel security. Notably, the side-channel analysis represents a standard procedure for evaluating novel countermeasures. Indeed, the [NIST FIPS-140v3](https://doi.org/10.6028/NIST.FIPS.140-3) standard enforces side-channel security as a mandatory step in the security validation of any novel software- and hardware-implemented cryptographic device. To this end, DFSDESYNCH is a valuable asset in strengthening real-world security by enabling researchers to identify and address potential weaknesses in cryptographic implementations. By promoting the creation of robust countermeasures, this dataset ultimately contributes to a more secure digital world.

As creating a high-quality training dataset is a fundamental requirement, the quality of DFS_DESYNCH sits on the time-consuming acquisition process that requires a clean-room acquisition setup and system-on-chip. Without considering the design time to obtain the implementation of the computing platform and the working acquisition setup, the time required by the acquisition procedure exceeded 40 hours.

Citation

@ARTICLE{10713265,
  author={Galli, Davide and Lattari, Francesco and Matteucci, Matteo and Zoni, Davide},
  journal={IEEE Transactions on Computers}, 
  title={A Deep Learning-Assisted Template Attack Against Dynamic Frequency Scaling Countermeasures}, 
  year={2025},
  volume={74},
  number={1},
  pages={293-306},
  doi={10.1109/TC.2024.3477997}
}

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Note

This work is part of [1] available online.

This repository is protected by copyright and licensed under the Open Data Commons License cc-by-4.0 file.

© 2024 hardware-fab

[1] D. Galli, F. Lattari, M. Matteucci and D. Zoni, "A Deep Learning-assisted Template Attack Against Dynamic Frequency Scaling Countermeasures," in IEEE Transactions on Computers, doi: 10.1109/TC.2024.3477997.