Jongbin-kr/VeriReason-reasoning-reproduced-1513_luna-medium

VeriReason reasoning reproduced (Luna medium)

This dataset is a deterministic sample of the locally updated reproduced VeriReason files.

• —Source files: train (1).jsonl, validation (1).jsonl
• —Sampling: independent shuffle then prefix slice, fixed seed 42
• —Splits: train 1513, validation 189
• —Original target dataset: Jongbin-kr/VeriReason-RTL-Coder7breasoning_tb (train 1513 / validation 189)
• —Schema: id, instruction, output, tb, tb_result
• —Quality checks: valid JSON, unique IDs, non-overlapping splits, one ordered think/answer block per output, no explicit failure markers in tb_result.
• —Normalization: removed only non-whitespace text after the final endmodule in 120 rows because it is not valid Verilog syntax.
• —A Verilog simulator was not available in the preparation environment, so full recompilation was not performed; tb_result was checked for explicit FAIL/ERROR/FATAL/TIMEOUT markers and testbench boundaries were statically checked.