datasets
Training and evaluation data, with the modality, task and licence stated up front. Listed live from the Hugging Face Hub.
nvlabs-verilogeval-v2-spec-to-rtlVerilogEvalv2 spec-to-rtl dataset from the VerilogEval paper. Paper: Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks Repo: https://github.com/NVlabs/verilog-eval).
Disclaimer: I am not the original author and uploaded this here only for convenience! Please refer to the original repo for any information.
nvlabs-verilogevalVerilogEval Human dataset from the VerilogEval paper.
Paper: https://arxiv.org/abs/2309.07544
Repo: https://github.com/NVlabs/verilog-eval?tab=License-1-ov-file).
Disclaimer: I am not the original author and uploaded this here only for convenience. Please refer to the original repo for any information.
semiconductor-rtl-verilog-chip-design-2026
⚡ Complete 2026 Semiconductor & RTL/Verilog Chip Design SFT & DPO Suite
An industry-first, production-grade reasoning and alignment corpus specifically engineered for fine-tuning Large Language Models on synthesizable SystemVerilog, FPGA/ASIC hardware design, and silicon signoff verification.
This release provides 1,000 verified preview pairs (from the complete 10,000 SFT & 2,500 DPO master suite) spanning 20 mission-critical silicon IP architectures, audited against IEEE… See the full description on the dataset page: https://huggingface.co/datasets/beatsprom/semiconductor-rtl-verilog-chip-design-2026.PyraNet-Verilog
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Authors: Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Paper link: https://arxiv.org/abs/2412.06947.
This dataset is built on top of the VeriBest dataset, which won
First Place
in the LLM4HWDesign contest at the ICCAD 2024 conference.
Dataset Summary
This dataset, introduced in our paper PyraNet: A Large Scale Hierarchical Verilog Dataset, addresses the limitations of existing Verilog datasets… See the full description on the dataset page: https://huggingface.co/datasets/bnadimi/PyraNet-Verilog.nvlabs-verilogeval-v2-completionVerilogEvalv2 complete-iccad-2023 dataset from the VerilogEval paper. Paper: Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks Repo: https://github.com/NVlabs/verilog-eval).
Disclaimer: I am not the original author and uploaded this here only for convenience! Please refer to the original repo for any information.
hardware-verilogeval-v2
hardware-verilogeval-v2
VerilogEval v2 - 471 Verilog evaluation problems
Dataset Overview
This dataset is part of a comprehensive collection of hardware design datasets for training and evaluating LLMs on Verilog/SystemVerilog code generation and hardware design tasks.
Files
verilog_eval_problems.json: 471 VerilogEval v2 problems
Usage
from datasets import load_dataset
# Load the dataset
dataset = load_dataset('AbiralArch/hardware-verilogeval-v2')… See the full description on the dataset page: https://huggingface.co/datasets/AbiralArch/hardware-verilogeval-v2.OSS_VerilogOriginal dataset size: 21725
Number of duplicate clusters: 2951
Files in duplicate cluster: 8054
Unique files in duplicate cluster: 3781
Filtered dataset size: 17452
Time to deduplicate dataset: 7.37
Size of deduplicated dataset: 17452, old dataset size 21725
verilog-training-data
Verilog and hardware design training data collection
Contents
cvdp_expert_problems.json: CVDP expert-level problems
cvdp_memory_problems.json: CVDP memory-focused problems
cvdp_processor_problems.json: CVDP processor design problems
Usage
from datasets import load_dataset
dataset = load_dataset('AbiralArch/verilog-training-data')
Statistics
Files: 3
Total Size: 10.1 MB
Uploaded: 2025-07-31 20:40:12
Files Available… See the full description on the dataset page: https://huggingface.co/datasets/AbiralArch/verilog-training-data.Verilog-Turkish-Dataset
Verilog Turkish Dataset
Overview
This dataset contains Turkish and English hardware design instructions paired with Verilog RTL implementations.
The dataset was created to support fine-tuning large language models for Verilog generation, especially for Turkish hardware design prompts.
It was primarily used to train the following model:
Model:Adel9st / Turkish-Verilog-Junior-Mid
The goal of this dataset is to help LLMs understand natural language hardware design requests… See the full description on the dataset page: https://huggingface.co/datasets/Adel9st/Verilog-Turkish-Dataset.verilogeval-v1-codev-qw-7b-results
VerilogEval v1 Results — yang-z/CodeV-QW-7B (Official CodeV Paper Fine-tune)
This dataset contains full benchmark results (aggregate scores + per-sample prompts and model responses) for evaluating the official CodeV paper fine-tune yang-z/CodeV-QW-7B on the VerilogEval v1 benchmark.
This is an independent reproduction of Table III of the CodeV paper (arXiv:2407.10424) using a fresh evaluation pipeline. All 6 metrics reproduce within ~1 point of the paper; 5/6 match or exceed paper… See the full description on the dataset page: https://huggingface.co/datasets/muratkarahan/verilogeval-v1-codev-qw-7b-results.LLM_4_Verilog
Verilog Instructions Dataset (15K)
A curated dataset of 15,000 Verilog HDL modules paired with structured natural language instructions, designed for training and evaluating code generation models on hardware description tasks.
Dataset Overview
Each entry pairs a complete Verilog module with a detailed, structured specification describing what the module should do -- suitable for instruction-tuned LLM training.
Property
Value
Samples
15,000
Format
JSONL… See the full description on the dataset page: https://huggingface.co/datasets/NOKHAB-Lab/LLM_4_Verilog.PyraNet-Verilog
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Authors: Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Paper link: https://arxiv.org/abs/2412.06947.
This dataset is built on top of the VeriBest dataset, which won
First Place
in the LLM4HWDesign contest at the ICCAD 2024 conference.
Dataset Summary
This dataset, introduced in our paper PyraNet: A Large Scale Hierarchical Verilog Dataset, addresses the limitations of existing Verilog… See the full description on the dataset page: https://huggingface.co/datasets/develoco/PyraNet-Verilog.smolified-verilog-krackhack
🤏 smolified-verilog-krackhack
Intelligence, Distilled.
This is a synthetic training corpus generated by the Smolify Foundry.
It was used to train the corresponding model smolify/smolified-verilog-krackhack.
📦 Asset Details
Origin: Smolify Foundry (Job ID: a13d194c)
Records: 1278
Type: Synthetic Instruction Tuning Data
⚖️ License & Ownership
This dataset is a sovereign asset owned by smolify.
Generated via Smolify.ai.
verilogeval-v1-qwen-base-results
VerilogEval v1 Baseline Results — Qwen/Qwen2.5-Coder-7B
This dataset contains full benchmark results (aggregate scores + per-sample prompts and model responses) for evaluating Qwen/Qwen2.5-Coder-7B on the VerilogEval v1 benchmark.
The evaluation follows the official VerilogEval v1 methodology (iverilog + vvp) with the official paper prompt format (detail_description as // comments followed by module header). Results are directly comparable to Table III of the CodeV paper… See the full description on the dataset page: https://huggingface.co/datasets/muratkarahan/verilogeval-v1-qwen-base-results.verilogeval-v1-codev-qwen-v2-results
VerilogEval v1 Results — muratkarahan/codev-qwen2.5-coder-7B-v2
This dataset contains full benchmark results (aggregate scores + per-sample prompts and model responses) for evaluating the fine-tuned model muratkarahan/codev-qwen2.5-coder-7B-v2 on the VerilogEval v1 benchmark.
The evaluation follows the official VerilogEval v1 methodology (iverilog + vvp) with the official paper prompt format (detail_description as // comments followed by module header). Results are directly… See the full description on the dataset page: https://huggingface.co/datasets/muratkarahan/verilogeval-v1-codev-qwen-v2-results.Verify-Verilog
VerifyVerilog
A rigorous benchmark for evaluating LLM-generated Verilog HDL. Built by adapting proven software benchmarks (AAPP, MBPP, HumanEval) to the hardware domain,
translate's 1,192 problems into hardware design tasks, measuring both compilation success and functional verification.
Repository: https://github.com/ani-ani/verifyverilog-dataset
Paper: TBD
Dataset Schema
Key
Description
task_id
Serial number identifier from the original programming… See the full description on the dataset page: https://huggingface.co/datasets/Ani-DNN/Verify-Verilog.VerilogEval-v2-NTU
VerilogEval-v2-NTU
This repository provides the patched version of VerilogEval-v2's dataset_spec-to-rtl, a benchmark designed to evaluate the capabilities of large language models in digital design and hardware description languages. The original VerilogEval-v2 dataset was developed by NVLabs and is available at https://github.com/NVlabs/verilog-eval under the MIT License.
All patches are located in the patches directory and are generated by create_patch.sh. The file… See the full description on the dataset page: https://huggingface.co/datasets/AS-SiliconMind/VerilogEval-v2-NTU.verilogeval-v1-codev-qc-7b-results
VerilogEval v1 Results — yang-z/CodeV-QC-7B (Official CodeV Paper Fine-tune)
This dataset contains full benchmark results (aggregate scores + per-sample prompts and model responses) for evaluating the official CodeV paper fine-tune yang-z/CodeV-QC-7B on the VerilogEval v1 benchmark.
This is an independent reproduction of the "CodeV-QC" row in Table III of the CodeV paper (arXiv:2407.10424), on the same Qwen2.5-Coder-7B base used by my own fine-tune. Four out of six metrics exceed… See the full description on the dataset page: https://huggingface.co/datasets/muratkarahan/verilogeval-v1-codev-qc-7b-results.verilog_dataset_near_dedupOriginal dataset size: 21725
Number of duplicate clusters: 2951
Files in duplicate cluster: 8054
Unique files in duplicate cluster: 3781
Filtered dataset size: 17452
Time to deduplicate dataset: 7.37
Size of deduplicated dataset: 17452, old dataset size 21725
F24-FFH-VerilogVerilog Generation training dataset - owned and maintained by Samuel Bush via the Secure and Trustworthy Hardware (SETH) Lab at Texas A&M University
Metrics:
Total Rows: ~222,000
Size of .JSON dataset: 17.8GB