datasets
Training and evaluation data, with the modality, task and licence stated up front. Listed live from the Hugging Face Hub.
hardware-verilogeval-v2
hardware-verilogeval-v2
VerilogEval v2 - 471 Verilog evaluation problems
Dataset Overview
This dataset is part of a comprehensive collection of hardware design datasets for training and evaluating LLMs on Verilog/SystemVerilog code generation and hardware design tasks.
Files
verilog_eval_problems.json: 471 VerilogEval v2 problems
Usage
from datasets import load_dataset
# Load the dataset
dataset = load_dataset('AbiralArch/hardware-verilogeval-v2')… See the full description on the dataset page: https://huggingface.co/datasets/AbiralArch/hardware-verilogeval-v2.hardware-cvdp-problems
Hardware Design AI Training Dataset
This dataset contains processed hardware design problems and Verilog code for training AI models.
Contents
CVDP Problems: 160 evaluation problems organized by domain and complexity
Training Data: Instruction-code pairs for hardware design
Metadata: Rich annotations for each problem
Usage
from datasets import load_dataset
dataset = load_dataset("AbiralArch/hardware-cvdp-problems")
Categories
Module Generation… See the full description on the dataset page: https://huggingface.co/datasets/AbiralArch/hardware-cvdp-problems.quantum-hardware-device-physics
Neura Parse — Quantum Hardware Device Physics: Qubit Design, Coherence, Control & Scaling
A physics- and engineering-deep vertical on how qubits are built, controlled, and scaled across superconducting, trapped-ion, neutral-atom, and spin modalities (plus emerging erasure/biased-noise qubits). Device-physics derivations, coherence-limit analyses, control-stack engineering, and 2025-2026 scaling/interconnect work, with QuTiP/scqubits simulation context — expanding the general… See the full description on the dataset page: https://huggingface.co/datasets/Neura-parse/quantum-hardware-device-physics.hardware-shailja-vgen
hardware-shailja-vgen
Shailja VGen Collection - 87 Verilog files
Dataset Overview
This dataset is part of a comprehensive collection of hardware design datasets for training and evaluating LLMs on Verilog/SystemVerilog code generation and hardware design tasks.
Files
vgen_files.json: 87 Verilog files from VGen framework
Usage
from datasets import load_dataset
# Load the dataset
dataset = load_dataset('AbiralArch/hardware-shailja-vgen')
# Access… See the full description on the dataset page: https://huggingface.co/datasets/AbiralArch/hardware-shailja-vgen.