datasets
Training and evaluation data, with the modality, task and licence stated up front. Listed live from the Hugging Face Hub.
verilog-instruct-60knvlabs-verilogeval-v2-spec-to-rtlVerilogEvalv2 spec-to-rtl dataset from the VerilogEval paper. Paper: Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks Repo: https://github.com/NVlabs/verilog-eval).
Disclaimer: I am not the original author and uploaded this here only for convenience! Please refer to the original repo for any information.
verilog-wavedrom
Verilog Wavedrom
A combination of verilog modules and their correspondig timing diagrams generated by wavedrom.
Dataset Details
A collection of wavedrom timing diagrams in PNG format representing verilog modules.
The Verilog modules were copied from shailja/Verilog_GitHub.The timing diagrams were generated by first generating testbenches for the individual verilog modules through the Verilog Testbench Generator from EDA Utils VlogTBGen.The resulting testbenches were… See the full description on the dataset page: https://huggingface.co/datasets/vkenbeek/verilog-wavedrom.nvlabs-verilogevalVerilogEval Human dataset from the VerilogEval paper.
Paper: https://arxiv.org/abs/2309.07544
Repo: https://github.com/NVlabs/verilog-eval?tab=License-1-ov-file).
Disclaimer: I am not the original author and uploaded this here only for convenience. Please refer to the original repo for any information.
semiconductor-rtl-verilog-chip-design-2026
⚡ Complete 2026 Semiconductor & RTL/Verilog Chip Design SFT & DPO Suite
An industry-first, production-grade reasoning and alignment corpus specifically engineered for fine-tuning Large Language Models on synthesizable SystemVerilog, FPGA/ASIC hardware design, and silicon signoff verification.
This release provides 1,000 verified preview pairs (from the complete 10,000 SFT & 2,500 DPO master suite) spanning 20 mission-critical silicon IP architectures, audited against IEEE… See the full description on the dataset page: https://huggingface.co/datasets/beatsprom/semiconductor-rtl-verilog-chip-design-2026.verilog-raw-100kverilog-instruct-deepseek-60knvlabs-verilogeval-v2-completionVerilogEvalv2 complete-iccad-2023 dataset from the VerilogEval paper. Paper: Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks Repo: https://github.com/NVlabs/verilog-eval).
Disclaimer: I am not the original author and uploaded this here only for convenience! Please refer to the original repo for any information.
RTL_verilog_verified_to_simulate_combinedOSS_VerilogOriginal dataset size: 21725
Number of duplicate clusters: 2951
Files in duplicate cluster: 8054
Unique files in duplicate cluster: 3781
Filtered dataset size: 17452
Time to deduplicate dataset: 7.37
Size of deduplicated dataset: 17452, old dataset size 21725
Verilog_VL
Dataset Card for Dataset Name
This dataset card aims to be a base template for new datasets. It has been generated using this raw template.
Dataset Details
Dataset Description
Curated by: [More Information Needed]
Funded by [optional]: [More Information Needed]
Shared by [optional]: [More Information Needed]
Language(s) (NLP): [More Information Needed]
License: [More Information Needed]
Dataset Sources [optional]
Repository: [More… See the full description on the dataset page: https://huggingface.co/datasets/Navyandsu/Verilog_VL.verilog_data-1-Cverilog-evalRTL_verilog_synthetic_Claude_4_verified_to_compile_FSMRTL_verilog_synthetic_Claude_3.7_verified_to_compileverilog_preprocessed_anonymizedRTL_verilog_claude_verified_to_simulate
RTL Verilog Synthetic Simulated Dataset (Merged & Deduplicated)
This dataset combines RTL Verilog code examples from both Claude 3.7 and Claude 4 datasets, keeping only the essential columns and working simulation examples.
Dataset Details
Sources: Claude 3.7 + Claude 4 RTL datasets
Filtering: Only successful simulations (simulation_status='PASS' or simulation_success=True)
Deduplication: MinHash with 0.8 similarity threshold on evolved_nl
No synthetic responses:… See the full description on the dataset page: https://huggingface.co/datasets/sonyashijin/RTL_verilog_claude_verified_to_simulate.verilog-fresh-testbench-datasetllama-3.1-8b-verilogRTL_verilog_synthetic_o3_verified_to_simulate_FSM
RTL Verilog Synthetic o3 Verified Hardware Design Dataset
A high-quality collection of 330 verified Verilog RTL design problems and solutions, synthetically generated using o3 and rigorously tested through compilation and simulation.
Dataset Summary
This dataset contains 330 unique Verilog problems across 5 fundamental RTL design categories, with 100% compilation and simulation success rate. All problems have been deduplicated using MinHash LSH techniques and verified… See the full description on the dataset page: https://huggingface.co/datasets/sonyashijin/RTL_verilog_synthetic_o3_verified_to_simulate_FSM.smolified-verilog-krackhack
🤏 smolified-verilog-krackhack
Intelligence, Distilled.
This is a synthetic training corpus generated by the Smolify Foundry.
It was used to train the corresponding model smolify/smolified-verilog-krackhack.
📦 Asset Details
Origin: Smolify Foundry (Job ID: a13d194c)
Records: 1278
Type: Synthetic Instruction Tuning Data
⚖️ License & Ownership
This dataset is a sovereign asset owned by smolify.
Generated via Smolify.ai.
tokenized-codeparrot-train-verilog
Dataset Card for "tokenized-codeparrot-train-verilog"
More Information needed
verilogVerilogEval-v2-NTU
VerilogEval-v2-NTU
This repository provides the patched version of VerilogEval-v2's dataset_spec-to-rtl, a benchmark designed to evaluate the capabilities of large language models in digital design and hardware description languages. The original VerilogEval-v2 dataset was developed by NVLabs and is available at https://github.com/NVlabs/verilog-eval under the MIT License.
All patches are located in the patches directory and are generated by create_patch.sh. The file… See the full description on the dataset page: https://huggingface.co/datasets/AS-SiliconMind/VerilogEval-v2-NTU.MG-Verilog
MG-Verilog
Reformatted version of MG-Verilog dataset.
Notice: I'm not the author of this work; please refer to the original dataset for more information.
Major changes:
Module headers are included in the code, so code can be compiled independently.
Chat template formats (e.g. [INST], <<SYS>>) are removed.
block_summary, detailed_global_summary, high_level_global_summary are separated and cleaned from description.
module_header and system_information are extracted from *_summary as… See the full description on the dataset page: https://huggingface.co/datasets/observerw/MG-Verilog.OSS_Verilog_Near_Deduprosetta_code_verilog Compilation of all the Verilog scripts from rosettacode.org.
The license for these scripts was found here
verilog_inferences_using_gemma2bVerilog_DB_readverilog-code-base