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Training and evaluation data, with the modality, task and licence stated up front. Listed live from the Hugging Face Hub.

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01AbiralArch /hardware-verilogeval-v2 hardware-verilogeval-v2 VerilogEval v2 - 471 Verilog evaluation problems Dataset Overview This dataset is part of a comprehensive collection of hardware design datasets for training and evaluating LLMs on Verilog/SystemVerilog code generation and hardware design tasks. Files verilog_eval_problems.json: 471 VerilogEval v2 problems Usage from datasets import load_dataset # Load the dataset dataset = load_dataset('AbiralArch/hardware-verilogeval-v2')… See the full description on the dataset page: https://huggingface.co/datasets/AbiralArch/hardware-verilogeval-v2.texttext-generationn<1K0 likes66 downloads1y agoHugging Face02rtl-llm /chisel-verilog-pairstext10K<n<100K3 likes52 downloads1y agoHugging Face03matthewdelorenzo /dpo_verilog_buggytext1K<n<10K0 likes36 downloads2y agoHugging Face04KSU-HW-SEC /Verilog_codetext10K<n<100K2 likes34 downloads2y agoHugging Face05ajn313 /verilog_datasettext100K<n<1M0 likes31 downloads3y agoHugging Face06rtl-llm /github_vhdl_verilogtext10K<n<100K0 likes28 downloads2y agoHugging Face07rtl-llm /PyMTL_Verilog_pairstext10K<n<100K0 likes23 downloads2y agoHugging Face08Ani-DNN /Verify-Veriloggated VerifyVerilog A rigorous benchmark for evaluating LLM-generated Verilog HDL. Built by adapting proven software benchmarks (AAPP, MBPP, HumanEval) to the hardware domain, translate's 1,192 problems into hardware design tasks, measuring both compilation success and functional verification. Repository: https://github.com/ani-ani/verifyverilog-dataset Paper: TBD Dataset Schema Key Description task_id Serial number identifier from the original programming… See the full description on the dataset page: https://huggingface.co/datasets/Ani-DNN/Verify-Verilog.texttext-generation1K<n<10K3 likes22 downloads8mo agoHugging Face09sjhhg /fpga_verilog Dataset Card for Dataset Name This dataset card aims to be a base template for new datasets. It has been generated using this raw template. Dataset Details Dataset Description Curated by: [More Information Needed] Funded by [optional]: [More Information Needed] Shared by [optional]: [More Information Needed] Language(s) (NLP): [More Information Needed] License: [More Information Needed] Dataset Sources [optional] Repository: [More… See the full description on the dataset page: https://huggingface.co/datasets/sjhhg/fpga_verilog.textquestion-answering1K<n<10K0 likes19 downloads1y agoHugging Face10sayanbhatia /verilog-testbenchtextn<1K0 likes13 downloads2y agoHugging Face11trizze /verilogTemptext1K<n<10K0 likes13 downloads2y agoHugging Face12markjiang /verilog_trainingtextn<1K0 likes12 downloads2y agoHugging Face13abi011020 /eda_verilog_code_200ktext100K<n<1M0 likes11 downloads1y agoHugging Face14tbd-lab /verilog-wavedrom-gpt-osstextn<1K0 likes11 downloads4mo agoHugging Face15dlastor /verilog_SFAtext100K<n<1M0 likes6 downloads1y agoHugging Face16abi011020 /eda_verilog_code_100ktext100K<n<1M0 likes5 downloads1y agoHugging Face17SamShrubo /F24-FFH-VeriloggatedVerilog Generation training dataset - owned and maintained by Samuel Bush via the Secure and Trustworthy Hardware (SETH) Lab at Texas A&M University Metrics: Total Rows: ~222,000 Size of .JSON dataset: 17.8GB texttext-generation100K<n<1M1 likes3 downloads2y agoHugging Face

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