basant307/AI_Governance_Project

1/*2Language: VHDL3Author: Igor Kalnitsky <igor@kalnitsky.org>4Contributors: Daniel C.K. Kho <daniel.kho@tauhop.com>, Guillaume Savaton <guillaume.savaton@eseo.fr>5Description: VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems.6Website: https://en.wikipedia.org/wiki/VHDL7Category: hardware8*/9 10function vhdl(hljs) {11  // Regular expression for VHDL numeric literals.12 13  // Decimal literal:14  const INTEGER_RE = '\\d(_|\\d)*';15  const EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;16  const DECIMAL_LITERAL_RE = INTEGER_RE + '(\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?';17  // Based literal:18  const BASED_INTEGER_RE = '\\w+';19  const BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';20 21  const NUMBER_RE = '\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';22 23  const KEYWORDS = [24    "abs",25    "access",26    "after",27    "alias",28    "all",29    "and",30    "architecture",31    "array",32    "assert",33    "assume",34    "assume_guarantee",35    "attribute",36    "begin",37    "block",38    "body",39    "buffer",40    "bus",41    "case",42    "component",43    "configuration",44    "constant",45    "context",46    "cover",47    "disconnect",48    "downto",49    "default",50    "else",51    "elsif",52    "end",53    "entity",54    "exit",55    "fairness",56    "file",57    "for",58    "force",59    "function",60    "generate",61    "generic",62    "group",63    "guarded",64    "if",65    "impure",66    "in",67    "inertial",68    "inout",69    "is",70    "label",71    "library",72    "linkage",73    "literal",74    "loop",75    "map",76    "mod",77    "nand",78    "new",79    "next",80    "nor",81    "not",82    "null",83    "of",84    "on",85    "open",86    "or",87    "others",88    "out",89    "package",90    "parameter",91    "port",92    "postponed",93    "procedure",94    "process",95    "property",96    "protected",97    "pure",98    "range",99    "record",100    "register",101    "reject",102    "release",103    "rem",104    "report",105    "restrict",106    "restrict_guarantee",107    "return",108    "rol",109    "ror",110    "select",111    "sequence",112    "severity",113    "shared",114    "signal",115    "sla",116    "sll",117    "sra",118    "srl",119    "strong",120    "subtype",121    "then",122    "to",123    "transport",124    "type",125    "unaffected",126    "units",127    "until",128    "use",129    "variable",130    "view",131    "vmode",132    "vprop",133    "vunit",134    "wait",135    "when",136    "while",137    "with",138    "xnor",139    "xor"140  ];141  const BUILT_INS = [142    "boolean",143    "bit",144    "character",145    "integer",146    "time",147    "delay_length",148    "natural",149    "positive",150    "string",151    "bit_vector",152    "file_open_kind",153    "file_open_status",154    "std_logic",155    "std_logic_vector",156    "unsigned",157    "signed",158    "boolean_vector",159    "integer_vector",160    "std_ulogic",161    "std_ulogic_vector",162    "unresolved_unsigned",163    "u_unsigned",164    "unresolved_signed",165    "u_signed",166    "real_vector",167    "time_vector"168  ];169  const LITERALS = [170    // severity_level171    "false",172    "true",173    "note",174    "warning",175    "error",176    "failure",177    // textio178    "line",179    "text",180    "side",181    "width"182  ];183 184  return {185    name: 'VHDL',186    case_insensitive: true,187    keywords: {188      keyword: KEYWORDS,189      built_in: BUILT_INS,190      literal: LITERALS191    },192    illegal: /\{/,193    contains: [194      hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.195      hljs.COMMENT('--', '$'),196      hljs.QUOTE_STRING_MODE,197      {198        className: 'number',199        begin: NUMBER_RE,200        relevance: 0201      },202      {203        className: 'string',204        begin: '\'(U|X|0|1|Z|W|L|H|-)\'',205        contains: [ hljs.BACKSLASH_ESCAPE ]206      },207      {208        className: 'symbol',209        begin: '\'[A-Za-z](_?[A-Za-z0-9])*',210        contains: [ hljs.BACKSLASH_ESCAPE ]211      }212    ]213  };214}215 216export { vhdl as default };217