LeonJia/mlab-synopsys-commitpack-sample
0156
1{2 "commit": "9204681",3 "old_file": "verilog/rtl/aes128/top/aes_top.sv",4 "new_file": "verilog/rtl/aes128/top/aes_top.sv",5 "old_contents": "/*********************************************************************************\n SPDX-FileCopyrightText: 2021 , Dinesh Annayya \n \n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License.\n SPDX-License-Identifier: Apache-2.0\n SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>\n\n***********************************************************************************/\n/**********************************************************************************\n \n AES Top Module \n \n Description \n AES Top module includes 128 bit aes_cipher & aes_inv_cipher \n \n To Do: \n 1. Integration 192/256 AES\n \n Author(s): \n - Dinesh Annayya, dinesh.annayya@gmail.com \n \n Revision : \n 0.0 - Oct 15, 2022 \n Initial Version picked from https://opencores.org/ocsvn/aes_core \n 0.1 - Nov 3, 2022\n Following changes are done\n 1. Wishbone register interface added\n 2. To reduce the design area of the aes_cipher and aes_inv_cipher\n A. aes_sbox used sequentially for 16 cycle for text compuation \n B. 4 cycle for next round key computation\n 0.2 - Nov 7, 2022\n Change the Reg I/F to DMEM interface for better RISCV core integration\n \n \n************************************************************************************/\n/************************************************************************************\n ECB Mode : ECB mode is the simplest block cipher mode of operation in existence. \n Its approach to multi-block plaintexts is to treat each block of the plaintext separately.\n encryption/decryption of one block has no effect on the encryption/decryption of any other. \n\n CBC Mode : CBC mode eliminates this problem by carrying information from the encryption or \n decryption of one block to the next.\n\n\n**************************************************************************************/\n\n\nmodule aes_top #( parameter WB_WIDTH = 32) (\n`ifdef USE_POWER_PINS\n input logic vccd1, // User area 1 1.8V supply\n input logic vssd1, // User area 1 digital ground\n`endif\n\n input logic mclk,\n input logic rst_n,\n\n input logic [3:0] cfg_cska,\n input logic wbd_clk_int,\n output logic wbd_clk_out,\n\n input logic dmem_req,\n input logic dmem_cmd,\n input logic [1:0] dmem_width,\n input logic [6:0] dmem_addr,\n input logic [31:0] dmem_wdata,\n output logic dmem_req_ack,\n output logic [31:0] dmem_rdata,\n output logic [1:0] dmem_resp,\n\n output logic idle // AES logic idle indication\n);\n\n\nlogic dmem_req_ack_enc;\nlogic [31:0] dmem_rdata_enc;\nlogic [1:0] dmem_resp_enc;\n\nlogic dmem_req_ack_decr;\nlogic [31:0] dmem_rdata_decr;\nlogic [1:0] dmem_resp_decr;\n\n\n// Encription local variable\nlogic cfg_enc_ld ; \nlogic enc_done ; \nlogic [127:0] cfg_enc_key ;\nlogic [127:0] cfg_enc_text_in ;\nlogic [127:0] enc_text_out ;\n\n// Decryption local variable\nlogic cfg_decr_kld ; \nlogic decr_done ; \nlogic [127:0] cfg_decr_key ; \nlogic [127:0] cfg_decr_text_in; \nlogic [127:0] decr_text_out ; \n\n\nassign dmem_req_ack = dmem_req_ack_enc | dmem_req_ack_decr;\n\nassign dmem_rdata = (dmem_resp_enc == 2'b01) ? dmem_rdata_enc : (dmem_resp_decr == 2'b01) ? dmem_rdata_decr : 'h0;\nassign dmem_resp = ((dmem_resp_enc == 2'b01) || (dmem_resp_decr == 2'b01)) ? 2'b01: 2'b00;\n\n//###################################\n// Clock Skey for WB clock\n//###################################\nclk_skew_adjust u_skew\n (\n`ifdef USE_POWER_PINS\n .vccd1 (vccd1 ),// User area 1 1.8V supply\n .vssd1 (vssd1 ),// User area 1 digital ground\n`endif\n\t .clk_in (wbd_clk_int ), \n\t .sel (cfg_cska ), \n\t .clk_out (wbd_clk_out ) \n );\n\n//###################################\n// Application Reset Synchronization\n//###################################\nreset_sync u_app_rst (\n\t .scan_mode (1'b0 ),\n .dclk (mclk ), // Destination clock domain\n\t .arst_n (rst_n ), // active low async reset\n .srst_n (rst_ss_n )\n );\n\n\n//###################################\n// Encription Register\n//###################################\naes_reg u_enc_reg(\n .mclk (mclk ),\n .rst_n (rst_ss_n ),\n\n .cfg_port_id (1'b0 ),\n\n .dmem_req (dmem_req ), \n .dmem_cmd (dmem_cmd ), \n .dmem_width (dmem_width ), \n .dmem_addr (dmem_addr ), \n .dmem_wdata (dmem_wdata ), \n .dmem_req_ack (dmem_req_ack_enc ), \n .dmem_rdata (dmem_rdata_enc ), \n .dmem_resp (dmem_resp_enc ), \n\n // Encription Reg Interface\n .cfg_aes_ld (cfg_enc_ld ),\n .aes_done (enc_done ),\n .cfg_key (cfg_enc_key ),\n .cfg_text_in (cfg_enc_text_in ),\n .text_out (enc_text_out ),\n\n .idle (idle )\n\n );\n\n\n//###################################\n// Encription core\n//###################################\naes_cipher_top u_cipher (\n .clk (mclk ), \n .rstn (rst_ss_n ), \n .ld (cfg_enc_ld ), \n .done (enc_done ), \n .key (cfg_enc_key ), \n .text_in (cfg_enc_text_in ), \n .text_out (enc_text_out )\n );\n\n//###################################\n// Decryption Register\n//###################################\naes_reg u_decr_reg(\n .mclk (mclk ),\n .rst_n (rst_ss_n ),\n\n .cfg_port_id (1'b1 ),\n\n .dmem_req (dmem_req ), \n .dmem_cmd (dmem_cmd ), \n .dmem_width (dmem_width ), \n .dmem_addr (dmem_addr ), \n .dmem_wdata (dmem_wdata ), \n .dmem_req_ack (dmem_req_ack_decr ), \n .dmem_rdata (dmem_rdata_decr ), \n .dmem_resp (dmem_resp_decr ), \n\n // Decription Reg Interface\n .cfg_aes_ld (cfg_decr_kld ),\n .aes_done (decr_done ),\n .cfg_key (cfg_decr_key ),\n .cfg_text_in (cfg_decr_text_in ),\n .text_out (decr_text_out )\n\n );\n\n//###################################\n// Decryption Core\n//###################################\naes_inv_cipher_top u_icipher (\n .clk (mclk ), \n .rstn (rst_ss_n ), \n .kld (cfg_decr_kld ), \n .ld (decr_kdone ), \n .kdone (decr_kdone ),\n .done (decr_done ), \n .key (cfg_decr_key ), \n .text_in (cfg_decr_text_in ), \n .text_out (decr_text_out ) \n );\n\nendmodule\n\n\n",6 "new_contents": "/*********************************************************************************\n SPDX-FileCopyrightText: 2021 , Dinesh Annayya \n \n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License.\n SPDX-License-Identifier: Apache-2.0\n SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>\n\n***********************************************************************************/\n/**********************************************************************************\n \n AES Top Module \n \n Description \n AES Top module includes 128 bit aes_cipher & aes_inv_cipher \n \n To Do: \n 1. Integration 192/256 AES\n \n Author(s): \n - Dinesh Annayya, dinesh.annayya@gmail.com \n \n Revision : \n 0.0 - Oct 15, 2022 \n Initial Version picked from https://opencores.org/ocsvn/aes_core \n 0.1 - Nov 3, 2022\n Following changes are done\n 1. Wishbone register interface added\n 2. To reduce the design area of the aes_cipher and aes_inv_cipher\n A. aes_sbox used sequentially for 16 cycle for text compuation \n B. 4 cycle for next round key computation\n 0.2 - Nov 7, 2022\n Change the Reg I/F to DMEM interface for better RISCV core integration\n \n \n************************************************************************************/\n/************************************************************************************\n ECB Mode : ECB mode is the simplest block cipher mode of operation in existence. \n Its approach to multi-block plaintexts is to treat each block of the plaintext separately.\n encryption/decryption of one block has no effect on the encryption/decryption of any other. \n\n CBC Mode : CBC mode eliminates this problem by carrying information from the encryption or \n decryption of one block to the next.\n\n\n**************************************************************************************/\n\n\nmodule aes_top #( parameter WB_WIDTH = 32) (\n`ifdef USE_POWER_PINS\n input logic vccd1, // User area 1 1.8V supply\n input logic vssd1, // User area 1 digital ground\n`endif\n\n input logic mclk,\n input logic rst_n,\n\n input logic [3:0] cfg_cska,\n input logic wbd_clk_int,\n output logic wbd_clk_out,\n\n input logic dmem_req,\n input logic dmem_cmd,\n input logic [1:0] dmem_width,\n input logic [6:0] dmem_addr,\n input logic [31:0] dmem_wdata,\n output logic dmem_req_ack,\n output logic [31:0] dmem_rdata,\n output logic [1:0] dmem_resp,\n\n output logic idle // AES logic idle indication\n);\n\n\nlogic rst_ss_n;\n\nlogic dmem_req_ack_enc;\nlogic [31:0] dmem_rdata_enc;\nlogic [1:0] dmem_resp_enc;\n\nlogic dmem_req_ack_decr;\nlogic [31:0] dmem_rdata_decr;\nlogic [1:0] dmem_resp_decr;\n\n\n// Encription local variable\nlogic cfg_enc_ld ; \nlogic enc_done ; \nlogic [127:0] cfg_enc_key ;\nlogic [127:0] cfg_enc_text_in ;\nlogic [127:0] enc_text_out ;\n\n// Decryption local variable\nlogic cfg_decr_kld ; \nlogic decr_done ; \nlogic [127:0] cfg_decr_key ; \nlogic [127:0] cfg_decr_text_in; \nlogic [127:0] decr_text_out ; \nlogic decr_kdone ;\n\nassign dmem_req_ack = dmem_req_ack_enc | dmem_req_ack_decr;\n\nassign dmem_rdata = (dmem_resp_enc == 2'b01) ? dmem_rdata_enc : (dmem_resp_decr == 2'b01) ? dmem_rdata_decr : 'h0;\nassign dmem_resp = ((dmem_resp_enc == 2'b01) || (dmem_resp_decr == 2'b01)) ? 2'b01: 2'b00;\n\n//###################################\n// Clock Skey for WB clock\n//###################################\nclk_skew_adjust u_skew\n (\n`ifdef USE_POWER_PINS\n .vccd1 (vccd1 ),// User area 1 1.8V supply\n .vssd1 (vssd1 ),// User area 1 digital ground\n`endif\n\t .clk_in (wbd_clk_int ), \n\t .sel (cfg_cska ), \n\t .clk_out (wbd_clk_out ) \n );\n\n//###################################\n// Application Reset Synchronization\n//###################################\nreset_sync u_app_rst (\n\t .scan_mode (1'b0 ),\n .dclk (mclk ), // Destination clock domain\n\t .arst_n (rst_n ), // active low async reset\n .srst_n (rst_ss_n )\n );\n\n\n//###################################\n// Encription Register\n//###################################\naes_reg u_enc_reg(\n .mclk (mclk ),\n .rst_n (rst_ss_n ),\n\n .cfg_port_id (1'b0 ),\n\n .dmem_req (dmem_req ), \n .dmem_cmd (dmem_cmd ), \n .dmem_width (dmem_width ), \n .dmem_addr (dmem_addr ), \n .dmem_wdata (dmem_wdata ), \n .dmem_req_ack (dmem_req_ack_enc ), \n .dmem_rdata (dmem_rdata_enc ), \n .dmem_resp (dmem_resp_enc ), \n\n // Encription Reg Interface\n .cfg_aes_ld (cfg_enc_ld ),\n .aes_done (enc_done ),\n .cfg_key (cfg_enc_key ),\n .cfg_text_in (cfg_enc_text_in ),\n .text_out (enc_text_out ),\n\n .idle (idle )\n\n );\n\n\n//###################################\n// Encription core\n//###################################\naes_cipher_top u_cipher (\n .clk (mclk ), \n .rstn (rst_ss_n ), \n .ld (cfg_enc_ld ), \n .done (enc_done ), \n .key (cfg_enc_key ), \n .text_in (cfg_enc_text_in ), \n .text_out (enc_text_out )\n );\n\n//###################################\n// Decryption Register\n//###################################\naes_reg u_decr_reg(\n .mclk (mclk ),\n .rst_n (rst_ss_n ),\n\n .cfg_port_id (1'b1 ),\n\n .dmem_req (dmem_req ), \n .dmem_cmd (dmem_cmd ), \n .dmem_width (dmem_width ), \n .dmem_addr (dmem_addr ), \n .dmem_wdata (dmem_wdata ), \n .dmem_req_ack (dmem_req_ack_decr ), \n .dmem_rdata (dmem_rdata_decr ), \n .dmem_resp (dmem_resp_decr ), \n\n // Decription Reg Interface\n .cfg_aes_ld (cfg_decr_kld ),\n .aes_done (decr_done ),\n .cfg_key (cfg_decr_key ),\n .cfg_text_in (cfg_decr_text_in ),\n .text_out (decr_text_out )\n\n );\n\n//###################################\n// Decryption Core\n//###################################\naes_inv_cipher_top u_icipher (\n .clk (mclk ), \n .rstn (rst_ss_n ), \n .kld (cfg_decr_kld ), \n .ld (decr_kdone ), \n .kdone (decr_kdone ),\n .done (decr_done ), \n .key (cfg_decr_key ), \n .text_in (cfg_decr_text_in ), \n .text_out (decr_text_out ) \n );\n\nendmodule\n\n\n",7 "subject": "lint clean-up\n",8 "message": "lint clean-up\n",9 "lang": "System Verilog",10 "license": "apache-2.0",11 "repos": "security_core",12 "returncode": 0,13 "stderr": ""14}