LeonJia/mlab-synopsys-commitpack-sample

1{2    "commit": "7abbc19",3    "old_file": "src/cpu/columns/1.sv",4    "new_file": "src/cpu/columns/1.sv",5    "old_contents": "`include \"../common.sv\"\n`include \"../actions.sv\"\nfunction void column_1(inout state_t state);\n  if (state.op[4]) begin\n    X_PTR(state, 1);\n    END(state, 6, 2);\n  end else begin\n    PTR_Y(state, 1);\n    END(state, 6, 2);\n  end\n  case (state.op[7:4])\n    'h0: ORA(state, 4);\n    'h1: ORA(state, 3);\n    'h2: AND(state, 4);\n    'h3: AND(state, 3);\n    'h4: EOR(state, 4);\n    'h5: EOR(state, 3);\n    'h6: ADC(state, 4);\n    'h7: ADC(state, 3);\n    'h8: STA(state, 4);\n    'h9: ADC(state, 3);\n    'hA: LDA(state, 4);\n    'hB: LDA(state, 3);\n    'hC: CMP(state, 4);\n    'hD: CMP(state, 3);\n    'hE: SBC(state, 4);\n    'hF: SBC(state, 3);\n  endcase\nendfunction\n",6    "new_contents": "`include \"../common.sv\"\n`include \"../actions.sv\"\nfunction void column_1(inout state_t state);\n  if (state.op[4]) begin\n    X_PTR(state, 1);\n    END(state, 6, 2);\n  end else begin\n    PTR_Y(state, 1);\n    END(state, 6, 2);\n  end\n  case (state.op[7:4])\n    'h0: ORA(state, 4);\n    'h1: ORA(state, 3);\n    'h2: AND(state, 4);\n    'h3: AND(state, 3);\n    'h4: EOR(state, 4);\n    'h5: EOR(state, 3);\n    'h6: ADC(state, 4);\n    'h7: ADC(state, 3);\n    'h8: STA(state, 4);\n    'h9: STA(state, 3);\n    'hA: LDA(state, 4);\n    'hB: LDA(state, 3);\n    'hC: CMP(state, 4);\n    'hD: CMP(state, 3);\n    'hE: SBC(state, 4);\n    'hF: SBC(state, 3);\n  endcase\nendfunction\n",7    "subject": "fixed column 1\n",8    "message": "fixed column 1\n",9    "lang": "System Verilog",10    "license": "mit",11    "repos": "nesv",12    "returncode": 0,13    "stderr": ""14}