LeonJia/mlab-synopsys-commitpack-sample
0156
1{2 "commit": "673e6c2",3 "old_file": "demo_1/src/my_env.sv",4 "new_file": "demo_1/src/my_env.sv",5 "old_contents": "// +FHDR----------------------------------------------------------------------------\n// Project Name : IC_Design\n// Device : ASIC\n// Author : zhouyuqian\n// Email : starrynightzyq@gmail.com\n// Website : https://zhouyuqian.com\n// Create On : 2022/05/09 14:45\n// Last Modified : 2022/05/09 14:45\n// File Name : my_env.sv\n// Description :\n// \n// \n// Copyright (c) 2022 .\n// ALL RIGHTS RESERVED\n// \n// ---------------------------------------------------------------------------------\n// Modification History:\n// Date By Version Change Description\n// ---------------------------------------------------------------------------------\n// 2022/05/09 zhouyuqian 1.0 Original\n// \n// -FHDR----------------------------------------------------------------------------\n\n`ifndef MY_ENV__SV\n`define MY_ENV__SV\n\n`include \"my_agent.sv\"\n`include \"my_model.sv\"\n`include \"my_scoreboard.sv\"\n`include \"my_sequence.sv\"\n\nclass my_env extends uvm_env;\n\n my_agent i_agt;\n my_agent o_agt;\n my_model mdl;\n my_scoreboard msd;\n uvm_tlm_analysis_fifo#(my_transcation) agt_mdl_fifo;\n uvm_tlm_analysis_fifo#(my_transcation) mdl_msd_fifo;\n uvm_tlm_analysis_fifo#(my_transcation) oagt_msd_fifo;\n\n function new(string name = \"my_env\", uvm_component parent);\n super.new(name, parent);\n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n i_agt = my_agent::type_id::create(\"i_agt\", this);\n o_agt = my_agent::type_id::create(\"o_agt\", this);\n i_agt.is_active = UVM_ACTIVE;\n o_agt.is_active = UVM_PASSIVE;\n mdl = my_model::type_id::create(\"mdl\", this);\n agt_mdl_fifo = new(\"agt_mdl_fifo\", this);\n mdl_msd_fifo = new(\"mdl_msd_fifo\", this);\n oagt_msd_fifo = new(\"oagt_msd_fifo\", this);\n msd = my_scoreboard::type_id::create(\"msd\", this);\n endfunction\n\n function void connect_phase(uvm_phase phase);\n super.connect_phase(phase);\n i_agt.ap.connect(agt_mdl_fifo.analysis_export);\n mdl.port.connect(agt_mdl_fifo.blocking_get_export);\n\n mdl.ap.connect(mdl_msd_fifo.analysis_export);\n msd.exp_port.connect(mdl_msd_fifo.blocking_get_export);\n\n o_agt.ap.connect(oagt_msd_fifo.analysis_export);\n msd.act_port.connect(oagt_msd_fifo.blocking_get_export);\n endfunction\n\n `uvm_component_utils(my_env);\n\n // extern task main_phase(uvm_phase phase);\n\nendclass\n\n// task my_env::main_phase(uvm_phase phase);\n // my_sequence seq;\n // phase.raise_objection(this);\n // seq = my_sequence::type_id::create(\"seq\");\n // seq.start(i_agt.sqr);\n // phase.drop_objection(this);\n// endtask\n\n`endif\n",6 "new_contents": "// +FHDR----------------------------------------------------------------------------\n// Project Name : IC_Design\n// Device : ASIC\n// Author : zhouyuqian\n// Email : starrynightzyq@gmail.com\n// Website : https://zhouyuqian.com\n// Create On : 2022/05/09 14:45\n// Last Modified : 2022/05/09 14:45\n// File Name : my_env.sv\n// Description :\n// \n// \n// Copyright (c) 2022 .\n// ALL RIGHTS RESERVED\n// \n// ---------------------------------------------------------------------------------\n// Modification History:\n// Date By Version Change Description\n// ---------------------------------------------------------------------------------\n// 2022/05/09 zhouyuqian 1.0 Original\n// \n// -FHDR----------------------------------------------------------------------------\n\n`ifndef MY_ENV__SV\n`define MY_ENV__SV\n\n`include \"my_agent.sv\"\n`include \"my_model.sv\"\n`include \"my_scoreboard.sv\"\n`include \"my_sequence.sv\"\n\nclass my_env extends uvm_env;\n\n my_agent i_agt;\n my_agent o_agt;\n my_model mdl;\n my_scoreboard scb;\n uvm_tlm_analysis_fifo#(my_transcation) agt_mdl_fifo;\n uvm_tlm_analysis_fifo#(my_transcation) mdl_scb_fifo;\n uvm_tlm_analysis_fifo#(my_transcation) oagt_scb_fifo;\n\n function new(string name = \"my_env\", uvm_component parent);\n super.new(name, parent);\n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n i_agt = my_agent::type_id::create(\"i_agt\", this);\n o_agt = my_agent::type_id::create(\"o_agt\", this);\n i_agt.is_active = UVM_ACTIVE;\n o_agt.is_active = UVM_PASSIVE;\n mdl = my_model::type_id::create(\"mdl\", this);\n agt_mdl_fifo = new(\"agt_mdl_fifo\", this);\n mdl_scb_fifo = new(\"mdl_scb_fifo\", this);\n oagt_scb_fifo = new(\"oagt_scb_fifo\", this);\n scb = my_scoreboard::type_id::create(\"scb\", this);\n endfunction\n\n function void connect_phase(uvm_phase phase);\n super.connect_phase(phase);\n i_agt.ap.connect(agt_mdl_fifo.analysis_export);\n mdl.port.connect(agt_mdl_fifo.blocking_get_export);\n\n mdl.ap.connect(mdl_scb_fifo.analysis_export);\n scb.exp_port.connect(mdl_scb_fifo.blocking_get_export);\n\n o_agt.ap.connect(oagt_scb_fifo.analysis_export);\n scb.act_port.connect(oagt_scb_fifo.blocking_get_export);\n endfunction\n\n `uvm_component_utils(my_env);\n\n // extern task main_phase(uvm_phase phase);\n\nendclass\n\n// task my_env::main_phase(uvm_phase phase);\n // my_sequence seq;\n // phase.raise_objection(this);\n // seq = my_sequence::type_id::create(\"seq\");\n // seq.start(i_agt.sqr);\n // phase.drop_objection(this);\n// endtask\n\n`endif\n",7 "subject": "change msd to scb (my_scoreboard)\n",8 "message": "change msd to scb (my_scoreboard)\n",9 "lang": "System Verilog",10 "license": "mit",11 "repos": "my-uvm-demo",12 "returncode": 0,13 "stderr": ""14}