LeonJia/mlab-synopsys-commitpack-sample

1{2    "commit": "87faaa6",3    "old_file": "src/core/alu.sv",4    "new_file": "src/core/alu.sv",5    "old_contents": "module alu (\n    input logic [31:0] srca,\n    input logic [31:0] srcb,\n    input logic [ 4:0] alucontrol,\n\n    output logic [31:0] res,\n    output logic flag\n);\n\n  always_comb begin\n    case (alucontrol)\n      5'b00000: begin\n        res  = srca;\n        flag = 0;\n      end\n      5'b00001: begin\n        res  = srcb + srca;\n        flag = 0;\n      end\n      5'b00010: begin\n        res  = srcb - srca;\n        flag = 0;\n      end\n      5'b00011: begin\n        res  = srcb & srca;\n        flag = 0;\n      end\n      5'b00100: begin\n        res  = srcb | srca;\n        flag = 0;\n      end\n      5'b00101: begin\n        res  = srcb ^ srca;\n        flag = 0;\n      end\n      5'b00110: begin\n        res  = srcb << srca;\n        flag = 0;\n      end\n      5'b00111: begin\n        res  = srcb >> srca;\n        flag = 0;\n      end\n      5'b01000: begin\n        res  = $signed(srcb) >>> srca;\n        flag = 0;\n      end\n      5'b01001: begin\n        res  = (srcb == srca) ? 1 : 0;\n        flag = (srcb == srca) ? 1 : 0;\n      end\n      5'b01010: begin\n        res  = (srcb != srca) ? 1 : 0;\n        flag = (srcb != srca) ? 1 : 0;\n      end\n      5'b01011: begin\n        res  = (srcb < srca) ? 1 : 0;\n        flag = (srcb < srca) ? 1 : 0;\n      end\n      5'b01100: begin\n        res  = (srcb > srca) ? 1 : 0;\n        flag = (srcb > srca) ? 1 : 0;\n      end\n      5'b01101: begin\n        res  = (srcb >= srca) ? 1 : 0;\n        flag = (srcb >= srca) ? 1 : 0;\n      end\n      5'b01110: begin\n        res  = ($signed(srcb) < $signed(srca)) ? 1 : 0;\n        flag = ($signed(srcb) < $signed(srca)) ? 1 : 0;\n      end\n      5'b01111: begin\n        res  = ($signed(srcb) > $signed(srca)) ? 1 : 0;\n        flag = ($signed(srcb) > $signed(srca)) ? 1 : 0;\n      end\n      5'b10000: begin\n        res  = ($signed(srcb) >= $signed(srca)) ? 1 : 0;\n        flag = ($signed(srcb) >= $signed(srca)) ? 1 : 0;\n      end\n      5'b10001: begin\n        res  = srcb << 16;\n        flag = 'x;\n      end\n      default: begin\n        res  = 'x;\n        flag = 'x;\n      end\n\n    endcase\n  end\n\n\nendmodule\n",6    "new_contents": "module alu (\n    input logic [31:0] srca,\n    input logic [31:0] srcb,\n    input logic [ 4:0] alucontrol,\n\n    output logic [31:0] res,\n    output logic flag\n);\n\n  always_comb begin\n    case (alucontrol)\n      5'b00000: begin\n        res  = srca;\n        flag = 0;\n      end\n      5'b00001: begin\n        res  = srcb + srca;\n        flag = 0;\n      end\n      5'b00010: begin\n        res  = srcb - srca;\n        flag = 0;\n      end\n      5'b00011: begin\n        res  = srcb & srca;\n        flag = 0;\n      end\n      5'b00100: begin\n        res  = srcb | srca;\n        flag = 0;\n      end\n      5'b00101: begin\n        res  = srcb ^ srca;\n        flag = 0;\n      end\n      5'b00110: begin\n        res  = srcb << srca;\n        flag = 0;\n      end\n      5'b00111: begin\n        res  = srcb >> srca;\n        flag = 0;\n      end\n      5'b01000: begin\n        res  = $signed(srcb) >>> srca;\n        flag = 0;\n      end\n      5'b01001: begin\n        res  = (srcb == srca) ? 1 : 0;\n        flag = (srcb == srca) ? 1 : 0;\n      end\n      5'b01010: begin\n        res  = (srcb != srca) ? 1 : 0;\n        flag = (srcb != srca) ? 1 : 0;\n      end\n      5'b01011: begin\n        res  = (srcb < srca) ? 1 : 0;\n        flag = (srcb < srca) ? 1 : 0;\n      end\n      5'b01100: begin\n        res  = (srcb > srca) ? 1 : 0;\n        flag = (srcb > srca) ? 1 : 0;\n      end\n      5'b01101: begin\n        res  = (srcb >= srca) ? 1 : 0;\n        flag = (srcb >= srca) ? 1 : 0;\n      end\n      5'b01110: begin\n        res  = ($signed(srcb) < $signed(srca)) ? 1 : 0;\n        flag = ($signed(srcb) < $signed(srca)) ? 1 : 0;\n      end\n      5'b01111: begin\n        res  = ($signed(srcb) > $signed(srca)) ? 1 : 0;\n        flag = ($signed(srcb) > $signed(srca)) ? 1 : 0;\n      end\n      5'b10000: begin\n        res  = ($signed(srcb) >= $signed(srca)) ? 1 : 0;\n        flag = ($signed(srcb) >= $signed(srca)) ? 1 : 0;\n      end\n      5'b10001: begin\n        res  = srcb << 16;\n        flag = 0;\n      end\n      default: begin\n        res  = 'x;\n        flag = 'x;\n      end\n\n    endcase\n  end\n\n\nendmodule\n",7    "subject": "Fix\n",8    "message": "Fix\n",9    "lang": "System Verilog",10    "license": "mit",11    "repos": "ktc32",12    "returncode": 0,13    "stderr": ""14}