LeonJia/mlab-synopsys-commitpack-sample

1{2    "commit": "e63163e",3    "old_file": "src/cpu.sv",4    "new_file": "src/cpu.sv",5    "old_contents": "`default_nettype none\nmodule noahgaertner_cpu (input logic [7:0] io_in,\n  output logic [7:0] io_out\n);\n  logic clock, reset;\n  assign clock = io_in[0];\n  assign reset = io_in[1];\n  typedef enum logic [3:0]{LOAD = 4'd0, STORE = 4'd1, ADD = 4'd2, MUL = 4'd3, WAIT = 4'd4, MAC = 4'd5, SUB = 4'd6, SHIFTL = 4'd7, SHIFTR = 4'd8, JUMPTOIF = 4'd9} prog_t;\n  prog_t prog[15:0];\n  logic [3:0] data [15:0];\n  enum logic [1:0] {LOADPROG=2'd0, LOADDATA=2'd1, SETRUNPT=2'd2,RUNPROG=2'd3} instruction;\n  assign instruction = io_in[3:2];\n  logic [3:0]   pc;\n  logic [3:0]   regval;\n  assign io_out = {regval, pc};\n  logic [3:0]  nextpc;\n  assign nextpc = pc + 1;\n  logic [3:0]  inputdata;\n  assign inputdata = io_in[7:4];\n  genvar i;\n\n  always_ff @(posedge clock) begin\n    if (reset) begin\n      case (instruction)\n        \n        LOADPROG: begin //loads a program into the program \"file\"\n          prog[pc] <= inputdata;\n          pc <= nextpc;\n        end\n        LOADDATA: begin //loads data into the data \"file\"\n          data[pc] <= inputdata;\n          pc <= nextpc;\n        end\n        SETRUNPT: begin //designed to be used right before run, but can also reset I guess?\n          pc <= inputdata;\n          regval <= 0;\n        end\n        RUNPROG: begin //run the program\n          case (prog[pc])\n            LOAD: begin \n              regval <= data[pc]; pc = nextpc; \n            end\n             //loads a value from the data file\n            STORE: begin \n              data[data[pc]] <= regval; pc <= nextpc;\n            end\n             //stores a value into the data file\n            ADD: begin \n              regval <= regval + data[pc]; pc <= nextpc;\n            end\n             //adds the value at the appropriate data address to the register\n            SUB: begin \n              pc <= regval - data[pc]; pc<= nextpc;\n            end\n             //subtracts the value at the appropriate addr from the register\n            WAIT: begin\n              pc <= nextpc; \n              end\n             //waits a clock cycle - not sure why you would ever, but whatever\n            MUL: begin \n              pc<= nextpc; regval <= regval * data[pc]; \n            end\n             //multiplies the register by the value at the appropriate addr\n            SHIFTL: begin \n              pc<= nextpc; regval <= regval << data[pc];\n            end\n              //shifts the register left by the value at the appropriate addr\n            SHIFTR: begin \n              pc<= nextpc; regval <= regval >> data[pc]; \n            end\n              //shifts the register right by the value at the appropriate addr\n            MAC: begin \n              pc<= nextpc; regval <= regval + (data[pc] * inputdata);\n            end\n              //multiplies the value at the appropriate addr by the input data and adds it to the register\n            JUMPTOIF: //jumps to value if input pin 7 is a one\n              //not unconditional to avoid looping forever\n            begin \n              if (inputdata[3]==1) begin \n                pc <= data[pc]; \n              end else begin \n                pc <= nextpc; \n                end\n            end\n          endcase\n        end\n      endcase\n    end\n    else begin\n      pc <= 0;\n      regval <= 0;\n      data[0] <= 4'd0;\n      data[1] <= 4'd0;\n      data[2] <= 4'd0;\n      data[3] <= 4'd0;\n      data[4] <= 4'd0;\n      data[5] <= 4'd0;\n      data[6] <= 4'd0;\n      data[7] <= 4'd0;\n      data[8] <= 4'd0;\n      data[9] <= 4'd0;\n      data[10] <= 4'd0;\n      data[11] <= 4'd0;\n      data[12] <= 4'd0;\n      data[13] <= 4'd0;\n      data[14] <= 4'd0;\n      data[15] <= 4'd0;\n      prog[0] <= 4'd0;\n      prog[1] <= 4'd0;\n      prog[2] <= 4'd0;\n      prog[3] <= 4'd0;\n      prog[4] <= 4'd0;\n      prog[5] <= 4'd0;\n      prog[6] <= 4'd0;\n      prog[7] <= 4'd0;\n      prog[8] <= 4'd0;\n      prog[9] <= 4'd0;\n      prog[10] <= 4'd0;\n      prog[11] <= 4'd0;\n      prog[12] <= 4'd0;\n      prog[13] <= 4'd0;\n      prog[14] <= 4'd0;\n      prog[15] <= 4'd0;\n    end\n  end\nendmodule\n",6    "new_contents": "`default_nettype none\nmodule noahgaertner_cpu (input logic [7:0] io_in,\n  output logic [7:0] io_out\n);\n  logic clock, reset;\n  assign clock = io_in[0];\n  assign reset = io_in[1];\n  typedef enum logic [3:0]{LOAD = 4'd0, STORE = 4'd1, ADD = 4'd2, MUL = 4'd3, WAIT = 4'd4, //MAC = 4'd5,\n   SUB = 4'd6, SHIFTL = 4'd7, SHIFTR = 4'd8, JUMPTOIF = 4'd9} prog_t;\n  prog_t prog[15:0];\n  logic [3:0] data [15:0];\n  enum logic [1:0] {LOADPROG=2'd0, LOADDATA=2'd1, SETRUNPT=2'd2,RUNPROG=2'd3} instruction;\n  assign instruction = io_in[3:2];\n  logic [3:0]   pc;\n  logic [3:0]   regval;\n  assign io_out = {regval, pc};\n  logic [3:0]  nextpc;\n  assign nextpc = pc + 1;\n  logic [3:0]  inputdata;\n  assign inputdata = io_in[7:4];\n  genvar i;\n\n  always_ff @(posedge clock) begin\n    if (reset) begin\n      case (instruction)\n        \n        LOADPROG: begin //loads a program into the program \"file\"\n          prog[pc] <= inputdata;\n          pc <= nextpc;\n        end\n        LOADDATA: begin //loads data into the data \"file\"\n          data[pc] <= inputdata;\n          pc <= nextpc;\n        end\n        SETRUNPT: begin //designed to be used right before run, but can also reset I guess?\n          pc <= inputdata;\n          regval <= 0;\n        end\n        RUNPROG: begin //run the program\n          case (prog[pc])\n            LOAD: begin \n              regval <= data[pc]; pc = nextpc; \n            end\n             //loads a value from the data file\n            STORE: begin \n              data[data[pc]] <= regval; pc <= nextpc;\n            end\n             //stores a value into the data file\n            ADD: begin \n              regval <= regval + data[pc]; pc <= nextpc;\n            end\n             //adds the value at the appropriate data address to the register\n            SUB: begin \n              pc <= regval - data[pc]; pc<= nextpc;\n            end\n             //subtracts the value at the appropriate addr from the register\n            WAIT: begin\n              pc <= nextpc; \n              end\n             //waits a clock cycle - not sure why you would ever, but whatever\n            MUL: begin \n              pc<= nextpc; regval <= regval * data[pc]; \n            end\n             //multiplies the register by the value at the appropriate addr\n            SHIFTL: begin \n              pc<= nextpc; regval <= regval << data[pc];\n            end\n              //shifts the register left by the value at the appropriate addr\n            SHIFTR: begin \n              pc<= nextpc; regval <= regval >> data[pc]; \n            end\n              //shifts the register right by the value at the appropriate addr\n            /* MAC: begin \n              pc<= nextpc; regval <= regval + (data[pc] * inputdata);\n            end */\n              //multiplies the value at the appropriate addr by the input data and adds it to the register\n            JUMPTOIF: //jumps to value if input pin 7 is a one\n              //not unconditional to avoid looping forever\n            begin \n              if (inputdata[3]==1) begin \n                pc <= data[pc]; \n              end else begin \n                pc <= nextpc; \n                end\n            end\n          endcase\n        end\n      endcase\n    end\n    else begin\n      pc <= 0;\n      regval <= 0;\n      data[0] <= 4'd0;\n      data[1] <= 4'd0;\n      data[2] <= 4'd0;\n      data[3] <= 4'd0;\n      data[4] <= 4'd0;\n      data[5] <= 4'd0;\n      data[6] <= 4'd0;\n      data[7] <= 4'd0;\n      data[8] <= 4'd0;\n      data[9] <= 4'd0;\n      data[10] <= 4'd0;\n      data[11] <= 4'd0;\n      data[12] <= 4'd0;\n      data[13] <= 4'd0;\n      data[14] <= 4'd0;\n      data[15] <= 4'd0;\n      prog[0] <= 4'd0;\n      prog[1] <= 4'd0;\n      prog[2] <= 4'd0;\n      prog[3] <= 4'd0;\n      prog[4] <= 4'd0;\n      prog[5] <= 4'd0;\n      prog[6] <= 4'd0;\n      prog[7] <= 4'd0;\n      prog[8] <= 4'd0;\n      prog[9] <= 4'd0;\n      prog[10] <= 4'd0;\n      prog[11] <= 4'd0;\n      prog[12] <= 4'd0;\n      prog[13] <= 4'd0;\n      prog[14] <= 4'd0;\n      prog[15] <= 4'd0;\n    end\n  end\nendmodule\n",7    "subject": "delete MAC\n",8    "message": "delete MAC\n",9    "lang": "System Verilog",10    "license": "apache-2.0",11    "repos": "f22-tt02-ngaertne",12    "returncode": 0,13    "stderr": ""14}