LeonJia/mlab-synopsys-commitpack-sample

1{2    "commit": "51c3813",3    "old_file": "src/cpu.sv",4    "new_file": "src/cpu.sv",5    "old_contents": "`default_nettype none\nmodule noahgaertner_cpu (\n    input  logic [7:0] io_in,\n    output logic [7:0] io_out\n);\n  logic clock, reset;\n  assign clock = io_in[0];  //clock\n  assign reset = io_in[1];  //reset to clear everything\n  typedef enum logic [3:0] {\n    LOAD = 4'd0, //loads a value from data file into operation register\n    STORE = 4'd1, //stores value from operation register to data file\n    ADD = 4'd2, //adds datac to operation register value\n    MUL = 4'd3, //multiples operation register value by datac\n    SUB = 4'd4, //subtracts datac from operation register value\n    SHIFTL = 4'd5, //shifts operation register value left by datac or 3, \n    //whichever is less\n    SHIFTR = 4'd6, //shifts operation register value right by datac or 3,\n    //whichever is less\n    JUMPTOIF = 4'd7, //jumps pc to data[value] if io_in[7] is a 1, else \n    //does nothing\n    LOGICAND = 4'd8,\n    //logical and between operation register value and datac\n    LOGICOR = 4'd9,\n    //logical or between operation register value and datac\n    EQUALS = 4'd10,\n    //equality check between operation register value and datac\n    NEQ = 4'd11,\n    //inequality check between operation register value and datac\n    BITAND = 4'd12,\n    //bitwise and between operation register value and datac    \n    BITOR = 4'd13,\n    //bitwise or between operation register value and datac\n    LOGICNOT = 4'd14,\n    //logical not on operation register value \n    BITNOT = 4'd15\n    //bitwise not on operation register value\n  } prog_t;\n  //yosys doesn't like it if i enum directly instead of typedef w/ memories for \n  //some reason\n  prog_t prog[15:0];  //program storage \"file\"\n  logic [3:0] data[15:0];  //data storage :file\n  enum logic [1:0] {\n    LOADPROG = 2'd0, //loads a program into the program \"file\"\n    LOADDATA = 2'd1, //loads data into the data \"file\"\n    SETRUNPT = 2'd2, //designed to be used right before run, but can also be used to input additional data i guess\n    RUNPROG  = 2'd3 //run the program\n  } instruction;\n  assign instruction = io_in[3:2];  //current instruction\n  logic [3:0] pc;  //program counter\n  logic [3:0] datac;\n  prog_t progc;\n  assign progc = prog[pc]; //prog at pc\n  assign datac = data[pc]; //data at pc\n  logic [3:0] regval;  //current value being operated on (accumulator)\n  assign io_out = {regval, pc};\n  logic [3:0] inputdata;\n  logic lastdata3;  //input data\n  assign inputdata = io_in[7:4];\n  logic [3:0] npc;\n  assign npc = pc+1;\n\n  always_ff @(posedge clock) begin\n    if (!reset) begin\n      lastdata3 <= inputdata[3];\n      case (instruction)\n\n        LOADPROG: begin  //loads a program into the program \"file\"\n          prog[pc] <= inputdata;\n          pc <= npc;\n        end\n        LOADDATA: begin  //loads data into the data \"file\"\n          data[pc] <= inputdata;\n          pc <= npc;\n        end\n        SETRUNPT: begin //designed to be used right before run, but can also be used to input additional data i guess\n          pc <= inputdata;\n        end\n        RUNPROG: begin  //run the program\n          case (progc)\n            LOAD: begin\n              //loads a value from the data file\n              regval <= datac;\n              pc <= npc;\n            end\n            STORE: begin\n              //stores a value into the data file\n              data[datac] <= regval;\n              pc <= npc;\n            end\n            ADD: begin\n              //adds the value at the appropriate data address to the register\n              regval <= regval + datac;\n              pc <= npc;\n            end\n            SUB: begin\n              //subtracts the value at the appropriate addr from the register\n              regval <= regval - datac;\n              pc <= npc;\n            end\n            MUL: begin\n              //multiplies the register by the value at the appropriate addr\n              pc <= npc;\n              regval <= regval * datac;\n            end\n            SHIFTL: begin\n              //shifts the register left by the value at the appropriate addr, \n              //or 3, whichever is less.\n              pc <= npc;\n              regval <= regval<<(datac&4'd3);\n            end\n            SHIFTR: begin\n              //shifts the register right by the value at the appropriate addr, \n              //or 3, whichever is less\n              pc <= npc;\n              regval <= regval >> (datac&4'd3);\n            end\n            JUMPTOIF: //jumps to value if input pin 7 is a one\n              //not unconditional to avoid looping forever\n              //weird external condition because of single-register/stack \n              //design due to space limits & effective max of 16 \n              //microinstructions, which is theoretically circumventable\n              //by serializing IO and reassembling, but that takes too much \n              //space\n            begin\n              pc <= (lastdata3) ? datac : npc;\n              regval <= regval;\n            end\n            LOGICAND: begin\n              //logical and between regval and datac\n              pc <= npc;\n              regval <= regval && datac;\n            end\n            LOGICOR: begin\n              //logical or between regval and datac\n              pc <= npc;\n              regval <= regval || datac;\n            end\n            EQUALS: begin\n              //equality check between regval and datac\n              pc <= npc;\n              regval <= (regval == datac);\n            end\n            NEQ: begin\n              //inequality check between regval and datac\n              pc <= npc;\n              regval <= (regval != datac);\n            end\n            BITAND: begin\n              //bitwise and between regval and datac\n              pc <= npc;\n              regval <= (regval & datac);\n            end\n            BITNOT: begin\n              //bitwise inversion on regval\n              pc<= npc;\n              regval <= ~(regval);\n            end\n            BITOR: begin\n              //bitwise or between regval and datac\n              pc<= npc;\n              regval <= (regval | datac);\n            end\n            LOGICNOT: begin\n              //logical NOT on regval\n              pc <= npc;\n              regval <= !regval;\n            end\n          endcase\n        end\n      endcase\n    end else begin\n      pc <= 0;\n      regval <= 0;\n      data[0] <= 4'd0;\n      data[1] <= 4'd0;\n      data[2] <= 4'd0;\n      data[3] <= 4'd0;\n      data[4] <= 4'd0;\n      data[5] <= 4'd0;\n      data[6] <= 4'd0;\n      data[7] <= 4'd0;\n      data[8] <= 4'd0;\n      data[9] <= 4'd0;\n      data[10] <= 4'd0;\n      data[11] <= 4'd0;\n      data[12] <= 4'd0;\n      data[13] <= 4'd0;\n      data[14] <= 4'd0;\n      data[15] <= 4'd0;\n      prog[0] <= 4'd0;\n      prog[1] <= 4'd0;\n      prog[2] <= 4'd0;\n      prog[3] <= 4'd0;\n      prog[4] <= 4'd0;\n      prog[5] <= 4'd0;\n      prog[6] <= 4'd0;\n      prog[7] <= 4'd0;\n      prog[8] <= 4'd0;\n      prog[9] <= 4'd0;\n      prog[10] <= 4'd0;\n      prog[11] <= 4'd0;\n      prog[12] <= 4'd0;\n      prog[13] <= 4'd0;\n      prog[14] <= 4'd0;\n      prog[15] <= 4'd0;\n      lastdata3 <= 1'd0;\n    end\n  end\nendmodule\n",6    "new_contents": "`default_nettype none\nmodule noahgaertner_cpu (\n    input  logic [7:0] io_in,\n    output logic [7:0] io_out\n);\n  logic clock, reset;\n  assign clock = io_in[0];  //clock\n  assign reset = io_in[1];  //reset to clear everything\n  typedef enum logic [3:0] {\n    LOAD = 4'd0, //loads a value from data file into operation register\n    STORE = 4'd1, //stores value from operation register to data file\n    ADD = 4'd2, //adds datac to operation register value\n    MUL = 4'd3, //multiples operation register value by datac\n    SUB = 4'd4, //subtracts datac from operation register value\n    SHIFTL = 4'd5, //shifts operation register value left by datac or 3, \n    //whichever is less\n    SHIFTR = 4'd6, //shifts operation register value right by datac or 3,\n    //whichever is less\n    JUMPTOIF = 4'd7, //jumps pc to data[value] if io_in[7] is a 1, else \n    //does nothing\n    LOGICAND = 4'd8,\n    //logical and between operation register value and datac\n    LOGICOR = 4'd9,\n    //logical or between operation register value and datac\n    EQUALS = 4'd10,\n    //equality check between operation register value and datac\n    NEQ = 4'd11,\n    //inequality check between operation register value and datac\n    BITAND = 4'd12,\n    //bitwise and between operation register value and datac    \n    BITOR = 4'd13,\n    //bitwise or between operation register value and datac\n    LOGICNOT = 4'd14,\n    //logical not on operation register value \n    BITNOT = 4'd15\n    //bitwise not on operation register value\n  } prog_t;\n  //yosys doesn't like it if i enum directly instead of typedef w/ memories for \n  //some reason\n  prog_t prog[15:0];  //program storage \"file\"\n  logic [3:0] data[15:0];  //data storage :file\n  enum logic [1:0] {\n    LOADPROG = 2'd0, //loads a program into the program \"file\"\n    LOADDATA = 2'd1, //loads data into the data \"file\"\n    SETRUNPT = 2'd2, //designed to be used right before run, but can also be used to input additional data i guess\n    RUNPROG  = 2'd3 //run the program\n  } instruction;\n  assign instruction = io_in[3:2];  //current instruction\n  logic [3:0] pc;  //program counter\n  logic [3:0] datac;\n  prog_t progc;\n  assign progc = prog[pc]; //prog at pc\n  assign datac = data[pc]; //data at pc\n  logic [3:0] regval;  //current value being operated on (accumulator)\n  assign io_out = {regval, pc};\n  logic [3:0] inputdata;\n  logic lastdata3;  //input data\n  assign inputdata = io_in[7:4];\n  logic [3:0] npc;\n  assign npc = pc+1;\n\n  always_ff @(posedge clock) begin\n    if (!reset) begin\n      lastdata3 <= inputdata[3];\n      case (instruction)\n\n        LOADPROG: begin  //loads a program into the program \"file\"\n          prog[pc] <= inputdata;\n          pc <= npc;\n        end\n        LOADDATA: begin  //loads data into the data \"file\"\n          data[pc] <= inputdata;\n          pc <= npc;\n        end\n        SETRUNPT: begin //designed to be used right before run, but can also be used to input additional data i guess\n          pc <= inputdata;\n        end\n        RUNPROG: begin  //run the program\n          case (progc)\n            LOAD: begin\n              //loads a value from the data file\n              regval <= datac;\n              pc <= npc;\n            end\n            STORE: begin\n              //stores a value into the data file\n              data[datac] <= regval;\n              pc <= npc;\n            end\n            ADD: begin\n              //adds the value at the appropriate data address to the register\n              regval <= regval + datac;\n              pc <= npc;\n            end\n            SUB: begin\n              //subtracts the value at the appropriate addr from the register\n              regval <= regval - datac;\n              pc <= npc;\n            end\n            MUL: begin\n              //multiplies the register by the value at the appropriate addr\n              pc <= npc;\n              regval <= regval * datac;\n            end\n            SHIFTL: begin\n              //shifts the register left by the value at the appropriate addr, \n              //or 3, whichever is less.\n              pc <= npc;\n              regval <= ((datac<4) ? regval<<datac : regval << 3);\n            end\n            SHIFTR: begin\n              //shifts the register right by the value at the appropriate addr, \n              //or 3, whichever is less\n              pc <= npc;\n              regval <= ((datac<4) ? regval>>datac : regval >> 3);\n            end\n            JUMPTOIF: //jumps to value if input pin 7 is a one\n              //not unconditional to avoid looping forever\n              //weird external condition because of single-register/stack \n              //design due to space limits & effective max of 16 \n              //microinstructions, which is theoretically circumventable\n              //by serializing IO and reassembling, but that takes too much \n              //space\n            begin\n              pc <= (lastdata3) ? datac : npc;\n              regval <= regval;\n            end\n            LOGICAND: begin\n              //logical and between regval and datac\n              pc <= npc;\n              regval <= regval && datac;\n            end\n            LOGICOR: begin\n              //logical or between regval and datac\n              pc <= npc;\n              regval <= regval || datac;\n            end\n            EQUALS: begin\n              //equality check between regval and datac\n              pc <= npc;\n              regval <= (regval == datac);\n            end\n            NEQ: begin\n              //inequality check between regval and datac\n              pc <= npc;\n              regval <= (regval != datac);\n            end\n            BITAND: begin\n              //bitwise and between regval and datac\n              pc <= npc;\n              regval <= (regval & datac);\n            end\n            BITNOT: begin\n              //bitwise inversion on regval\n              pc<= npc;\n              regval <= ~(regval);\n            end\n            BITOR: begin\n              //bitwise or between regval and datac\n              pc<= npc;\n              regval <= (regval | datac);\n            end\n            LOGICNOT: begin\n              //logical NOT on regval\n              pc <= npc;\n              regval <= !regval;\n            end\n          endcase\n        end\n      endcase\n    end else begin\n      pc <= 0;\n      regval <= 0;\n      data[0] <= 4'd0;\n      data[1] <= 4'd0;\n      data[2] <= 4'd0;\n      data[3] <= 4'd0;\n      data[4] <= 4'd0;\n      data[5] <= 4'd0;\n      data[6] <= 4'd0;\n      data[7] <= 4'd0;\n      data[8] <= 4'd0;\n      data[9] <= 4'd0;\n      data[10] <= 4'd0;\n      data[11] <= 4'd0;\n      data[12] <= 4'd0;\n      data[13] <= 4'd0;\n      data[14] <= 4'd0;\n      data[15] <= 4'd0;\n      prog[0] <= 4'd0;\n      prog[1] <= 4'd0;\n      prog[2] <= 4'd0;\n      prog[3] <= 4'd0;\n      prog[4] <= 4'd0;\n      prog[5] <= 4'd0;\n      prog[6] <= 4'd0;\n      prog[7] <= 4'd0;\n      prog[8] <= 4'd0;\n      prog[9] <= 4'd0;\n      prog[10] <= 4'd0;\n      prog[11] <= 4'd0;\n      prog[12] <= 4'd0;\n      prog[13] <= 4'd0;\n      prog[14] <= 4'd0;\n      prog[15] <= 4'd0;\n      lastdata3 <= 1'd0;\n    end\n  end\nendmodule\n",7    "subject": "routing congestion fix\n",8    "message": "routing congestion fix\n",9    "lang": "System Verilog",10    "license": "apache-2.0",11    "repos": "f22-tt02-ngaertne",12    "returncode": 0,13    "stderr": ""14}