LeonJia/mlab-synopsys-commitpack-sample

1{2    "commit": "00245ea",3    "old_file": "test_union.sv",4    "new_file": "test_union.sv",5    "old_contents": "///////////////////////////////////////////////////////////////////////////////\n// R5P: load/store unit\n///////////////////////////////////////////////////////////////////////////////\n// Copyright 2022 Iztok Jeras\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n//     http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n///////////////////////////////////////////////////////////////////////////////\n\nmodule r5p_lsu\n  import riscv_isa_pkg::*;\n(\n  // instruction input\n  input  logic [32-1:0] ins,\n  // partially decoded output\n  output logic  [5-1:0] rd ,  // register destination\n  output logic  [5-1:0] rs1,  // register source 1\n  output logic  [5-1:0] rs2,  // register source 2\n  output logic [12-1:0] imm   // immediate\n);\n\nop32_t dec;\n\nassign dec = op32_t'(ins);\n\nassign rd  = dec.r.rd ;\nassign rs1 = dec.r.rs1;\nassign rs2 = dec.r.rs2;\nassign imm = dec.i.imm_11_0;\n\nendmodule: r5p_lsu\n",6    "new_contents": "///////////////////////////////////////////////////////////////////////////////\n// R5P: load/store unit\n///////////////////////////////////////////////////////////////////////////////\n// Copyright 2022 Iztok Jeras\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n//     http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n///////////////////////////////////////////////////////////////////////////////\n\nmodule test_union\n  import riscv_isa_pkg::*;\n(\n  // instruction input\n  input  logic [32-1:0] ins,\n  // partially decoded output\n  output logic  [5-1:0] rd ,  // register destination\n  output logic  [5-1:0] rs1,  // register source 1\n  output logic  [5-1:0] rs2,  // register source 2\n  output logic [12-1:0] imm   // immediate\n);\n\nop32_t dec;\n\nassign dec = op32_t'(ins);\n\nassign rd  = dec.r.rd ;\nassign rs1 = dec.r.rs1;\nassign rs2 = dec.r.rs2;\nassign imm = dec.i.imm_11_0;\n\nendmodule: test_union\n",7    "subject": "fixed module name\n",8    "message": "fixed module name\n",9    "lang": "System Verilog",10    "license": "apache-2.0",11    "repos": "UHDM-tests",12    "returncode": 0,13    "stderr": ""14}