LeonJia/mlab-synopsys-commitpack-sample
0156
1{2 "commit": "aacbde2",3 "old_file": "step_1_dut_core.sv",4 "new_file": "step_1_dut_core.sv",5 "old_contents": "////////////////////////////////////////////////////////////////////////////////\n// Welcome!\n////////////////////////////////////////////////////////////////////////////////\n// You made a great choice installing Sigasi Studio, and now you are ready to\n// unlock its power.\n//\n// This demo file will guide you through your first steps. In about ten\n// minutes you will have learned the basics of how Sigasi helps you work\n// with Verilog and SystemVerilog files. This tutorial also covers more advanced\n// topics, which you can explore at your own pace.\n//\n// TODO In the (System)Verilog files of this project, follow the comments that\n// are marked 'TODO'.\n//\n// TODO Double-click the tab of this editor to switch to full screen editing.\n////////////////////////////////////////////////////////////////////////////////\n\nmodule dut_core(\n output logic [7:0] pixel_out,\n input [7:0] pixel_pp,\n input [7:0] pixel_p0,\n input [7:0] pixel_pm,\n input [7:0] pixel_0p,\n input [7:0] pixel_0m,\n input [7:0] pixel_mp,\n input [7:0] pixel_m0,\n input [7:0] pixel_mm,\n input on_edge,\n input clock,\n input reset);\n\n wire logic signed [15:0] gradx; // X gradient\n wire logic signed [15:0] grady; // Y gradient\n wire logic signed [15:0] gradsq; // XY gradient, squared\n logic signed [9:0] gradx_r; // X gradient, buffered\n logic signed [9:0] grady_r; // Y gradient, buffered\n\n // Calculate the X, Y and XY(squared) gradients\n assign gradx = (pixel_mp - pixel_pp) + 2 * (pixel_m0 - pixel_p0) + (pixel_mm - pixel_pm);\n assign grady = (pixel_mp - pixel_mm) + 2 * (pixel_0p - pixel_0m) + (pixel_pp - pixel_pm);\n assign gradsq = (gradx_r * gradx_r) + (grady_r * grady_r);\n\n always @(posedge clock) begin\n gradx_r = gradx;\n grady_r = grady;\n end\n\n always_ff @(posedge clock) begin\n if (on_edge == 1'b1)\n begin\n pixel_out <= 'b0;\n end\n else\n begin\n pixel_out <= gradsq[15:8];\n end\n end\nendmodule\n\nmodule counter #(WIDTH = 16) (\n input clk,\n input rst,\n input start,\n input enable,\n input [(WIDTH-1):0] endvalue,\n output [(WIDTH-1):0] count,\n output logic near_end,\n output logic on_edge\n);\n\n logic [(WIDTH-1):0] count_val;\n\n always @(posedge clk) begin\n if (rst == 1'b1)\n begin\n count_val = 'b0;\n near_end = 1'b0;\n end\n else if (start == 1'b1)\n begin\n count_val = 'b0;\n near_end = 1'b0; // assuming that endvalue > 1\n end\n else if (enable == 1'b1 && count_val < endvalue)\n begin\n near_end = (count_val == (endvalue - 2))?1'b1:1'b0;\n count_val += 1;\n end\n end;\n\n assign count = count_val;\n\n always @(count, endvalue) begin\n if (count == 0 || count == endvalue)\n on_edge = 1'b1;\n else\n on_edge = 1'b0;\n end\n\nendmodule\n",6 "new_contents": "////////////////////////////////////////////////////////////////////////////////\n// Welcome!\n////////////////////////////////////////////////////////////////////////////////\n// You made a great choice installing Sigasi Studio, and now you are ready to\n// unlock its power.\n//\n// This demo file will guide you through your first steps. In about ten\n// minutes you will have learned the basics of how Sigasi helps you work\n// with Verilog and SystemVerilog files. This tutorial also covers more advanced\n// topics, which you can explore at your own pace.\n//\n// TODO In the (System)Verilog files of this project, follow the comments that\n// are marked 'TODO'.\n//\n// TODO Double-click the tab of this editor to switch to full screen editing.\n////////////////////////////////////////////////////////////////////////////////\n\nmodule dut_core(\n output logic [7:0] pixel_out,\n input [7:0] pixel_pp,\n input [7:0] pixel_p0,\n input [7:0] pixel_pm,\n input [7:0] pixel_0p,\n input [7:0] pixel_0m,\n input [7:0] pixel_mp,\n input [7:0] pixel_m0,\n input [7:0] pixel_mm,\n input on_edge,\n input clock,\n input reset;\n\n wire logic signed [15:0] gradx; // X gradient\n wire logic signed [15:0] grady; // Y gradient\n wire logic signed [15:0] gradsq; // XY gradient, squared\n logic signed [9:0] gradx_r; // X gradient, buffered\n logic signed [9:0] grady_r; // Y gradient, buffered\n\n // Calculate the X, Y and XY(squared) gradients\n assign gradx = (pixel_mp - pixel_pp) + 2 * (pixel_m0 - pixel_p0) + (pixel_mm - pixel_pm);\n assign grady = (pixel_mp - pixel_mm) + 2 * (pixel_0p - pixel_0m) + (pixel_pp - pixel_pm);\n assign gradsq = (gradx_r * gradx_r) + (grady_r * grady_r);\n\n always @(posedge clock) begin\n gradx_r = gradx;\n grady_r = grady;\n end\n\n always_ff @(posedge clock) begin\n if (on_edge == 1'b1)\n begin\n pixel_out <= 'b0;\n end\n else\n begin\n pixel_out <= gradsq[15:8];\n end\n end\nendmodule\n\nmodule counter #(WIDTH = 16) (\n input clk,\n input rst,\n input start,\n input enable,\n input [(WIDTH-1):0] endvalue,\n output [(WIDTH-1):0] count,\n output logic near_end,\n output logic on_edge\n);\n\n logic [(WIDTH-1):0] count_val;\n\n always @(posedge clk) begin\n if (rst == 1'b1)\n begin\n count_val = 'b0;\n near_end = 1'b0;\n end\n else if (start == 1'b1)\n begin\n count_val = 'b0;\n near_end = 1'b0; // assuming that endvalue > 1\n end\n else if (enable == 1'b1 && count_val < endvalue)\n begin\n near_end = (count_val == (endvalue - 2))?1'b1:1'b0;\n count_val += 1;\n end\n end;\n\n assign count = count_val;\n\n always @(count, endvalue) begin\n if (count == 0 || count == endvalue)\n on_edge = 1'b1;\n else\n on_edge = 1'b0;\n end\n\nendmodule\n",7 "subject": "introduce error\n",8 "message": "introduce error\n",9 "lang": "System Verilog",10 "license": "bsd-3-clause",11 "repos": "Sigasi_CLI_in_CI_demo",12 "returncode": 0,13 "stderr": ""14}