LeonJia/mlab-synopsys-commitpack-sample

1{2    "commit": "2172065",3    "old_file": "step_4_pixel_testbench.sv",4    "new_file": "step_4_pixel_testbench.sv",5    "old_contents": "// Module pixel_testbench implements a first testbench for the design under test.\n\nmodule pixel_testbench();\n    reg clk;\n    reg rst;\n    reg start;\n\n    logic [11:0] size_x = 40, size_y = 40;\n    logic [23:0] count;\n    typedef enum {IDLE, RUNNING, READY} t_feeder_states;\n    t_feeder_states feeder_state;\n    // Feed data into the DUT\n    always @(posedge clk) begin\n        if (rst == 1'b1) begin\n            feeder_state = IDLE;\n            pixel_in = 0;\n            count = 0;\n        end\n        else begin\n            pixel_in = 0;\n            case (feeder_state)\n                IDLE:\n                if (start) begin\n                    feeder_state = RUNNING;\n                    pixel_in = input_pixel;\n                    count = 1;\n                end\n                RUNNING:\n                if (count < size_x * size_y) begin\n                    pixel_in = input_pixel;\n                    count += 1;\n                end\n                else\n                    feeder_state = READY;\n                    //default : feeder_state = IDLE;\n                READY: begin\n                    $display(\"All done\");\n                    feeder_state = IDLE;\n                end\n            endcase\n        end\n    end\n\n    dut_top dut_top_instance (\n        .clk(clk),\n        .rst(rst),\n        .start(start),\n        .size_x(size_x),\n        .size_y(size_y),\n        .pixel_in(pixel_in),\n        .pixel_out(pixel_out),\n        .pixel_valid(pixel_valid)\n    );\n\n    // Clock generator\n    always #5 begin\n        clk = ~clk;\n    end\n\n    // Drive `reset` and `start`\n    drive_rst_start drive_rst_start_instance (\n        .rst(rst),\n        .start(start)\n    );\n\nendmodule\n",6    "new_contents": "// Module pixel_testbench implements a first testbench for the design under test.\n\nmodule pixel_testbench();\n    logic clk;\n    reg rst; // @suppress \"'logic' should be used instead of 'reg'\"\n    reg start; // @suppress \"'logic' should be used instead of 'reg'\"\n\n    logic [11:0] size_x = 40, size_y = 40;\n    logic [23:0] count;\n    typedef enum {IDLE, RUNNING, READY} t_feeder_states;\n    t_feeder_states feeder_state;\n    // Feed data into the DUT\n    always @(posedge clk) begin\n        if (rst == 1'b1) begin\n            feeder_state = IDLE;\n            pixel_in = 0;\n            count = 0;\n        end\n        else begin\n            pixel_in = 0;\n            case (feeder_state)\n                IDLE:\n                if (start) begin\n                    feeder_state = RUNNING;\n                    pixel_in = input_pixel;\n                    count = 1;\n                end\n                RUNNING:\n                if (count < size_x * size_y) begin\n                    pixel_in = input_pixel;\n                    count += 1;\n                end\n                else\n                    feeder_state = READY;\n                    //default : feeder_state = IDLE;\n                READY: begin\n                    $display(\"All done\");\n                    feeder_state = IDLE;\n                end\n            endcase\n        end\n    end\n\n    dut_top dut_top_instance (\n        .clk(clk),\n        .rst(rst),\n        .start(start),\n        .size_x(size_x),\n        .size_y(size_y),\n        .pixel_in(pixel_in),\n        .pixel_out(pixel_out),\n        .pixel_valid(pixel_valid)\n    );\n\n    // Clock generator\n    always #5 begin\n        clk = ~clk;\n    end\n\n    // Drive `reset` and `start`\n    drive_rst_start drive_rst_start_instance (\n        .rst(rst),\n        .start(start)\n    );\n\nendmodule\n",7    "subject": "Some warnings corrected or suppressed\n",8    "message": "Some warnings corrected or suppressed\n",9    "lang": "System Verilog",10    "license": "bsd-3-clause",11    "repos": "Sigasi_CLI_in_CI_demo",12    "returncode": 0,13    "stderr": ""14}