LeonJia/mlab-synopsys-commitpack-sample
0156
1{2 "commit": "20fe085",3 "old_file": "verilog/rans_decoder.sv",4 "new_file": "verilog/rans_decoder.sv",5 "old_contents": "\nmodule rans_decoder\n#(\n parameter SYMBOL_WIDTH = 4,\n parameter LOG_M = 10, // ideally we make M a power of 2\n parameter CONST_T = 1,\n parameter BIN_PARALLELISM = 8\n)(\n input clk,\n input rst_n,\n input config_en,\n input [SYMBOL_WIDTH-1:0] config_symbol,\n input [LOG_H-1:0] config_freq,\n input [LOG_M-1:0] config_cumul,\n input [LOG_M-1:0] partial_enc,\n output reg [SYMBOL_WIDTH-1:0] symbol,\n output reg [ENC_MAX_LEN_WIDTH-1:0] enc_len\n);\n localparam EM = $exp2(LOG_M);\n localparam LOG_H = LOG_M * $clog2(CONST_T) + 1;\n localparam P_WIDTH = $clog2(BIN_PARALLELISM);\n\n logic [STATE_WIDTH-1:0] state;\n logic [LOG_M-1:0] cumul_array [NUM_SYMBOLS-1:0];\n logic search_one_hot [BIN_PARALLELISM-1:0];\n logic [P_WIDTH-1:0] depth;\n logic [P_WIDTH-1:0] search_found;\n\n // LUTs for freq[s], cumul[s], and cumul_rev[cumul]\n symbol_lut #(\n .SYMBOL_WIDTH(SYMBOL_WIDTH),\n .SYMBOL_COUNT(NUM_SYMBOLS),\n .OUTPUT_WIDTH(LOG_H)\n ) freq_lut (\n .clk(clk),\n .rst_n(rst_n),\n .config_en(config_en),\n .config_symbol(),\n .config_output(),\n .symbol(symbol),\n .out(freq)\n );\n\n symbol_lut #(\n .SYMBOL_WIDTH(SYMBOL_WIDTH),\n .SYMBOL_COUNT(NUM_SYMBOLS),\n .OUTPUT_WIDTH(LOG_M)\n ) cumul_lut (\n .clk(clk),\n .rst_n(rst_n),\n .config_en(config_en),\n .config_symbol(),\n .config_output(),\n .symbol(symbol),\n .out(cumul)\n );\n\n symbol_lut #(\n .SYMBOL_WIDTH(LOG_M),\n .SYMBOL_COUNT(NUM_SYMBOLS),\n .OUTPUT_WIDTH(SYMBOL_WIDTH)\n ) cumul_rev (\n .clk(clk),\n .rst_n(rst_n),\n .config_en(config_en),\n .config_symbol(),\n .config_output(),\n .symbol(match),\n .out(symbol)\n );\n\n always_comb begin\n for (int i = 0; i < BIN_PARALLELISM; i++) begin\n search_one_hot[i] = cumul_array[i << depth] > state[LOG_M-1:0];\n end\n search_found = 0;\n for (int i = 0; i < BIN_PARALLELISM; i++) begin\n if (search_one_hot[i]) begin\n search_found = i\n end\n end\n end\n\n always_ff @(posedge clk) begin\n if (rst_n && !config_en) begin\n if (state) begin\n // normal operation\n \n // decode step logic\n state <= (state >> LOG_M)*freq + state[LOG_M-1:0] - cumul;\n\n // expand state logic\n // NOTE: VERIFY BITLENGTHS\n end else begin\n // state just reset, copy in partial state\n state <= partial_enc;\n\n end else begin\n // reset\n state <= 0;\n enc <= 0;\n enc_len <= 0;\n end\n end\n\nendmodule\n",6 "new_contents": "\nmodule rans_decoder\n#(\n parameter SYMBOL_WIDTH = 4,\n parameter LOG_M = 10, // ideally we make M a power of 2\n parameter CONST_T = 1,\n parameter BIN_PARALLELISM = 8\n)(\n input clk,\n input rst_n,\n input config_en,\n input [SYMBOL_WIDTH-1:0] config_symbol,\n input [LOG_H-1:0] config_freq,\n input [LOG_M-1:0] config_cumul,\n input [LOG_M-1:0] partial_enc,\n output reg [SYMBOL_WIDTH-1:0] symbol,\n output reg [ENC_MAX_LEN_WIDTH-1:0] enc_len\n);\n localparam EM = $exp2(LOG_M);\n localparam LOG_H = LOG_M * $clog2(CONST_T) + 1;\n localparam P_WIDTH = $clog2(BIN_PARALLELISM);\n\n logic [STATE_WIDTH-1:0] state;\n logic [LOG_M-1:0] cumul_array [NUM_SYMBOLS-1:0];\n logic search_one_hot [BIN_PARALLELISM-1:0];\n logic [P_WIDTH-1:0] depth;\n logic [P_WIDTH-1:0] search_found;\n\n // LUTs for freq[s], cumul[s], and cumul_rev[cumul]\n symbol_lut #(\n .SYMBOL_WIDTH(SYMBOL_WIDTH),\n .SYMBOL_COUNT(NUM_SYMBOLS),\n .OUTPUT_WIDTH(LOG_H)\n ) freq_lut (\n .clk(clk),\n .rst_n(rst_n),\n .config_en(config_en),\n .config_symbol(),\n .config_output(),\n .symbol(symbol),\n .out(freq)\n );\n\n symbol_lut #(\n .SYMBOL_WIDTH(SYMBOL_WIDTH),\n .SYMBOL_COUNT(NUM_SYMBOLS),\n .OUTPUT_WIDTH(LOG_M)\n ) cumul_lut (\n .clk(clk),\n .rst_n(rst_n),\n .config_en(config_en),\n .config_symbol(),\n .config_output(),\n .symbol(symbol),\n .out(cumul)\n );\n\n symbol_lut #(\n .SYMBOL_WIDTH(LOG_M),\n .SYMBOL_COUNT(NUM_SYMBOLS),\n .OUTPUT_WIDTH(SYMBOL_WIDTH)\n ) cumul_rev (\n .clk(clk),\n .rst_n(rst_n),\n .config_en(config_en),\n .config_symbol(),\n .config_output(),\n .symbol(match),\n .out(symbol)\n );\n\n always_comb begin\n for (int i = 0; i < BIN_PARALLELISM; i++) begin\n search_one_hot[i] = cumul_array[i << depth] > state[LOG_M-1:0];\n end\n search_found = 0;\n for (int i = 0; i < BIN_PARALLELISM; i++) begin\n if (search_one_hot[i]) begin\n search_found = i\n end\n end\n end\n\n always_ff @(posedge clk) begin\n if (rst_n && !config_en) begin\n if (state) begin\n // normal operation\n \n // decode step logic\n state <= (state >> LOG_M)*freq + state[LOG_M-1:0] - cumul;\n\n // expand state logic\n // NOTE: VERIFY BITLENGTHS\n end else begin\n // state just reset, copy in partial state\n state <= partial_enc;\n\n end else begin\n // reset\n state <= 0;\n enc <= 0;\n enc_len <= 0;\n end\n end\n\nendmodule\n",7 "subject": "Merge branch 'main' of github.com:somewhatdistracted/EE274-Project\n",8 "message": "Merge branch 'main' of github.com:somewhatdistracted/EE274-Project\n",9 "lang": "System Verilog",10 "license": "mit",11 "repos": "EE274-Project",12 "returncode": 0,13 "stderr": ""14}