LeonJia/mlab-synopsys-commitpack-sample
0156
1{2 "commit": "dbeb395",3 "old_file": "sim/testbench_3.sv",4 "new_file": "sim/testbench_3.sv",5 "old_contents": "`timescale 1ns / 1ps\n`default_nettype none\n\n`include \"src/iverilog_hack_thresh.svh\"\n\n/******************************COMMANDS*********************************\n\niverilog -g2012 -o sim/testbench_3.out sim/testbench_3.sv src/xilinx_single_port_ram_read_first.v src/find_corners.sv src/card_isolator.sv\n\nvvp sim/testbench_3.out\n\n************************************************************************/\n\nmodule testbench_3;\n\n logic clk; \n logic rst; \n\n logic find_corners_flag; \n logic [15:0] pixel_data; \n\n logic [16:0] addr; \n logic data_valid_out; \n logic [239:0] line_cache_out; \n\n logic [7:0] right_edge; \n logic [7:0] left_edge; \n logic [8:0] top_edge; \n logic [8:0] bot_edge; \n\n xilinx_single_port_ram_read_first #(\n .RAM_WIDTH(16), // Specify RAM data width\n .RAM_DEPTH(76800), // Specify RAM depth (number of entries) 1.2Mbits \n .RAM_PERFORMANCE(\"LOW_LATENCY\"), // Select \"HIGH_PERFORMANCE\" or \"LOW_LATENCY\" \n .INIT_FILE(`FPATH(king_of_clubs_thresh_processed.mem))) // Specify name/location of RAM initialization file if using one (leave blank if not)\n card_input (\n .addra(addr), // Address bus, width determined from RAM_DEPTH\n .dina(16'b0), // RAM input data, width determined from RAM_WIDTH\n .clka(clk), // Clock\n .wea(1'b0), // Write enable\n .ena(1'b1), // RAM Enable, for additional power savings, disable port when not in use\n .rsta(rst), // Output reset (does not affect memory contents)\n .regcea(1'b1), // Output register enable\n .douta(pixel_data) // RAM output data, width determined from RAM_WIDTH\n );\n\n find_corners #(\n .HEIGHT(320), \n .WIDTH(240))\n corner_finder (\n .clk_in(clk), \n .rst_in(rst), \n .find_corners_flag(find_corners_flag),\n .x_center(8'd114),\n .y_center(9'd153), \n .pixel_data_in(pixel_data), \n .addr_out(addr), \n .data_valid_out(data_valid_out),\n .right_edge(right_edge), \n .left_edge(left_edge), \n .top_edge(top_edge), \n .bot_edge(bot_edge)\n );\n\n always begin\n #5; //every 5 ns switch...so period of clock is 10 ns...100 MHz clock\n clk = !clk;\n end\n\n //initial block...this is our test simulation\n initial begin\n $dumpfile(\"sim/testbench_3.vcd\");\n $dumpvars(0, testbench_3);\n $display(\"Starting Sim\"); //print nice message\n\n find_corners_flag = 1'b0; \n clk = 1'b1; \n rst = 1'b0; \n #10; \n rst = 1'b1; \n #10; \n rst = 1'b0; \n #10; \n find_corners_flag = 1'b1;\n #10;\n find_corners_flag = 1'b0;\n #50000; \n $display(\"Right: %d , Left: %d , Top: %d , Bot: %d \", right_edge, left_edge, top_edge, bot_edge);\n\n $display(\"Finishing Sim\"); //print nice message\n $finish;\n end\n\nendmodule \n\n`default_nettype wire",6 "new_contents": "`timescale 1ns / 1ps\n`default_nettype none\n\n`include \"src/iverilog_hack_thresh.svh\"\n\n/******************************COMMANDS*********************************\n\niverilog -g2012 -o sim/testbench_3.out sim/testbench_3.sv src/xilinx_single_port_ram_read_first.v src/find_corners.sv src/card_isolator.sv\n\nvvp sim/testbench_3.out\n\n************************************************************************/\n\nmodule testbench_3;\n\n logic clk; \n logic rst; \n\n logic find_corners_flag; \n logic [15:0] pixel_data; \n\n logic [16:0] addr; \n logic data_valid_out; \n logic [239:0] line_cache_out; \n\n logic [7:0] right_edge; \n logic [7:0] left_edge; \n logic [8:0] top_edge; \n logic [8:0] bot_edge; \n\n xilinx_single_port_ram_read_first #(\n .RAM_WIDTH(16), // Specify RAM data width\n .RAM_DEPTH(76800), // Specify RAM depth (number of entries) 1.2Mbits \n .RAM_PERFORMANCE(\"LOW_LATENCY\"), // Select \"HIGH_PERFORMANCE\" or \"LOW_LATENCY\" \n .INIT_FILE(`FPATH(king_of_clubs_thresh_processed.mem))) // Specify name/location of RAM initialization file if using one (leave blank if not)\n card_input (\n .addra(addr), // Address bus, width determined from RAM_DEPTH\n .dina(16'b0), // RAM input data, width determined from RAM_WIDTH\n .clka(clk), // Clock\n .wea(1'b0), // Write enable\n .ena(1'b1), // RAM Enable, for additional power savings, disable port when not in use\n .rsta(rst), // Output reset (does not affect memory contents)\n .regcea(1'b1), // Output register enable\n .douta(pixel_data) // RAM output data, width determined from RAM_WIDTH\n );\n\n find_corners #(\n .HEIGHT(320), \n .WIDTH(240))\n corner_finder (\n .clk_in(clk), \n .rst_in(rst), \n .find_corners_flag(find_corners_flag),\n .x_center(8'd114),\n .y_center(9'd153), \n .pixel_data_in(pixel_data), \n .addr_out(addr), \n .data_valid_out(data_valid_out),\n .right_edge(right_edge), \n .left_edge(left_edge), \n .top_edge(top_edge), \n .bot_edge(bot_edge)\n );\n\n always begin\n #5; //every 5 ns switch...so period of clock is 10 ns...100 MHz clock\n clk = !clk;\n end\n\n //initial block...this is our test simulation\n initial begin\n $dumpfile(\"sim/testbench_3.vcd\");\n $dumpvars(0, testbench_3);\n $display(\"Starting Sim\"); //print nice message\n\n find_corners_flag = 1'b0; \n clk = 1'b1; \n rst = 1'b0; \n #10; \n rst = 1'b1; \n #10; \n rst = 1'b0; \n #10; \n find_corners_flag = 1'b1;\n #10;\n find_corners_flag = 1'b0;\n #50010; \n $display(\"Right: %d , Left: %d , Top: %d , Bot: %d \", right_edge, left_edge, top_edge, bot_edge);\n\n $display(\"Finishing Sim\"); //print nice message\n $finish;\n end\n\nendmodule \n\n`default_nettype wire",7 "subject": "Update testbench_3.sv\n",8 "message": "Update testbench_3.sv\n",9 "lang": "System Verilog",10 "license": "mit",11 "repos": "6205-fp",12 "returncode": 0,13 "stderr": ""14}