IDEALLab/power_electronics_v1

1---2pretty_name: EngiBench PowerElectronics v13license: cc-by-nc-sa-4.04task_categories:5- tabular-regression6tags:7- engineering-design8- multi-objective-optimization9- circuit-simulation10- ngspice11- engibench12size_categories:13- 10K<n<100K14dataset_info:15  features:16  - name: dataset_schema_version17    dtype: int6418  - name: split19    dtype: string20  - name: source_index21    dtype: int6422  - name: design_sha25623    dtype: string24  - name: initial_design25    sequence: float6426  - name: v0_DcGain27    dtype: float6428  - name: v0_Voltage_Ripple29    dtype: float6430  - name: source_dataset_id31    dtype: string32  - name: source_dataset_revision33    dtype: string34  - name: problem_version35    dtype: int6436  - name: engibench_git_commit37    dtype: string38  - name: netlist_sha25639    dtype: string40  - name: simulator_version41    dtype: string42  - name: simulator_sha25643    dtype: string44  - name: simulator_platform_system45    dtype: string46  - name: simulator_platform_machine47    dtype: string48  - name: container_sha25649    dtype: string50  - name: output_voltage_mean51    dtype: float6452  - name: output_voltage_peak_to_peak53    dtype: float6454  - name: dc_gain55    dtype: float6456  - name: dc_gain_error57    dtype: float6458  - name: relative_voltage_ripple59    dtype: float6460  - name: simulation_valid61    dtype: bool62  - name: objectives_valid63    dtype: bool64  - name: simulation_status65    dtype: string66  - name: error_type67    dtype: string68  - name: error_message69    dtype: string70  splits:71  - name: train72    num_bytes: 668258473    num_examples: 967674  - name: val75    num_bytes: 190412576    num_examples: 276577  - name: test78    num_bytes: 95378379    num_examples: 138380  download_size: 253660381  dataset_size: 954049282configs:83- config_name: default84  data_files:85  - split: train86    path: data/train-*.parquet87  - split: val88    path: data/val-*.parquet89  - split: test90    path: data/test-*.parquet91---92 93# EngiBench PowerElectronics v194 95PowerElectronics v1 is a simulator-frozen EngiBench dataset for data-driven96engineering design. It re-simulates the exact 13,824 input designs and preserves97the train/validation/test membership from98[`IDEALLab/power_electronics_v0`](https://huggingface.co/datasets/IDEALLab/power_electronics_v0),99but it is a **new benchmark** and does not claim to reproduce the v0 labels.100 101The canonical backend is ngspice 44.2 on Linux x86_64 in a pinned Apptainer102image. v1 corrects the objective semantics, retains signed physical103measurements, and records the source, code, netlist, simulator, and container104fingerprints in every row.105 106## Loading107 108Pin the release tag in reproducible experiments:109 110```python111from datasets import load_dataset112 113dataset = load_dataset(114    "IDEALLab/power_electronics_v1",115    revision="v1.0.0",116)117```118 119## Splits and simulation status120 121| Split | Rows | Status |122| --- | ---: | --- |123| train | 9,676 | 9,674 `ok`; 2 `invalid_measurements` |124| validation (`val`) | 2,765 | 2,764 `ok`; 1 `invalid_measurements` |125| test | 1,383 | 1,383 `ok` |126 127The three invalid simulator results are retained at `train[4309]`,128`train[5960]`, and `val[223]`. Their unavailable measurements and objectives129are `null`; they are never replaced with zero, imputed, clipped, or removed.130 131Consumers should retain every row and use `objectives_valid` as a mask when a132numeric regression loss requires objective labels. Invalid rows may also be133used to model the simulator-failure region. Evaluation must report the number134of valid and invalid rows rather than silently dropping failures.135 136All finite values, including negative signed measurements and very large137relative-ripple values near zero mean voltage, remain unchanged.138 139## v1 objectives140 141The stored physical measurements are:142 143- signed mean output voltage, `output_voltage_mean`;144- peak-to-peak output voltage, `output_voltage_peak_to_peak`.145 146With a 1,000 V source, v1 derives the signed gain and two minimization147objectives:148 149```text150dc_gain = output_voltage_mean / 1000151dc_gain_error = abs(dc_gain - 0.25)152relative_voltage_ripple = output_voltage_peak_to_peak / abs(output_voltage_mean)153```154 155If the simulator does not return finite measurements, the derived objectives156are `null` and the validity/status fields identify the failure. A zero mean157voltage would similarly make relative ripple unavailable rather than assigning158an artificial value.159 160## Fields161 162### Identity and source mapping163 164- `dataset_schema_version`: schema version for this row format.165- `split`, `source_index`: exact v0 split membership and row index.166- `design_sha256`: stable checksum of `initial_design`.167- `initial_design`: the original 20-dimensional v0 design.168- `v0_DcGain`, `v0_Voltage_Ripple`: immutable v0 labels retained only for169  direct comparison.170- `source_dataset_id`, `source_dataset_revision`: exact v0 source.171- `problem_version`: EngiBench problem version (`1`).172 173### Reproducibility174 175- `engibench_git_commit`, `netlist_sha256`;176- `simulator_version`, `simulator_sha256`;177- `simulator_platform_system`, `simulator_platform_machine`;178- `container_sha256`.179 180### Measurements, objectives, and validity181 182- `output_voltage_mean`, `output_voltage_peak_to_peak`, `dc_gain`;183- `dc_gain_error`, `relative_voltage_ripple`;184- `simulation_valid`, `objectives_valid`, `simulation_status`;185- `error_type`, `error_message` for caught simulator exceptions.186 187## Frozen provenance188 189| Component | Identity |190| --- | --- |191| Source dataset | `IDEALLab/power_electronics_v0` |192| Source revision | `5c4adb2ec5cfc71794988b1297a7ff8ffe59daa5` |193| EngiBench commit | `64e6107d44349e67e031cad36633c1af26817784` |194| EngiBench review | [IDEALLab/EngiBench#279](https://github.com/IDEALLab/EngiBench/pull/279) |195| Simulator | ngspice 44.2, Linux x86_64 |196| ngspice binary SHA-256 | `11a4334ee90509f5edfdceef541711a34a1943d26a14cf0928ac8d5947b72374` |197| Apptainer SIF SHA-256 | `40816f203b7e1c68ae37f4d9353bd302486d77988b98733c021f1ff71f48ae02` |198| Container definition SHA-256 | `20675ae0ab31723bae9dd5881d04fcff6e7e08047898b3cbf4e6595dfb705695` |199| Netlist SHA-256 | `7a3c9f061993ceddd605394cd03d899b1933370cc0cd38b48606c1d0c23d13a7` |200 201The exact original v0 runtime cannot be confirmed. An archived notebook202contains evidence for Windows/x86_64 and ngspice 36, while an ngspice 44.2203ARM64 Mac reproduction is much closer to the published v0 labels than the204corresponding Linux x86_64 reproduction. Because operating system, simulator205version, compiler, and build also differ, the latter is evidence consistent206with ARM but is not proof of the original architecture.207 208Do not combine v0 and v1 labels or silently train on one backend and verify on209another. Cross-backend comparisons should be explicit experiments.210 211## Generation and audit212 213The `provenance/` directory contains:214 215- the 24 original generation manifests;216- the strict 13,824-row audit report;217- the JSONL-to-Parquet semantic conversion report;218- the container recipe and exact Python dependency freeze;219- the Euler Slurm generation script and both audit/conversion scripts.220 221The Parquet conversion sorts every split by `source_index`. Its report verifies222that every value and `null` round-trips exactly from the audited JSONL source.223 224## Limitations225 226- Results are specific to the frozen ngspice binary and container fingerprint.227- Relative ripple can become extremely large when the absolute mean voltage is228  close to zero. These finite values are intentional and are not clipped.229- Three designs do not have finite simulator measurements on the canonical230  backend. Their explicit invalid status is part of the benchmark.231- The v0 labels are provided for comparison, not as additional v1 targets.232 233## Citation234 235```bibtex236@inproceedings{felten_engibench_2025,237  title = {{EngiBench}: {A} {Framework} for {Data}-{Driven} {Engineering} {Design} {Research}},238  author = {Felten, Florian and Apaza, Gabriel and B\"{a}unlich, Gerhard and Diniz, Cashen and Dong, Xuliang and Drake, Arthur and Habibi, Milad and Hoffman, Nathaniel J. and Keeler, Matthew and Massoudi, Soheyl and VanGessel, Francis G. and Fuge, Mark},239  booktitle = {Proceedings of the 39th Conference on Neural Information Processing Systems ({NeurIPS} 2025)},240  year = {2025}241}242```243